3535#define DMAR_ICS_REG 0x9cU /* Invalidation complete status register */
3636#define DMAR_IRTA_REG 0xb8U /* Interrupt remapping table addr register */
3737
38- #define DMAR_VER_MAJOR (v ) (((v) & 0xf0U) >> 4)
39- #define DMAR_VER_MINOR (v ) ((v) & 0x0fU)
38+ static inline uint8_t dmar_ver_major (uint64_t version )
39+ {
40+ return ((version & 0xf0UL ) >> 4U );
41+ }
42+
43+ static inline uint8_t dmar_ver_minor (uint64_t version )
44+ {
45+ return (version & 0x0fUL );
46+ }
4047
4148/*
4249 * Decoding Capability Register
@@ -282,14 +289,30 @@ static inline uint8_t iommu_ecap_pds(uint64_t ecap)
282289#define DMA_CCMD_GLOBAL_INVL (((uint64_t)1UL) << 61)
283290#define DMA_CCMD_DOMAIN_INVL (((uint64_t)2UL) << 61)
284291#define DMA_CCMD_DEVICE_INVL (((uint64_t)3UL) << 61)
285- #define DMA_CCMD_FM (m ) (((uint64_t)((m) & 0x3UL)) << 32)
292+ static inline uint64_t dma_ccmd_fm (uint8_t fm )
293+ {
294+ return (((uint64_t )(fm & 0x3U )) << 32U );
295+ }
296+
286297#define DMA_CCMD_MASK_NOBIT 0UL
287298#define DMA_CCMD_MASK_1BIT 1UL
288299#define DMA_CCMD_MASK_2BIT 2UL
289300#define DMA_CCMD_MASK_3BIT 3UL
290- #define DMA_CCMD_SID (s ) (((uint64_t)((s) & 0xffffUL)) << 16)
291- #define DMA_CCMD_DID (d ) ((uint64_t)((d) & 0xffffUL))
292- #define DMA_CCMD_GET_CAIG_32 (v ) (((uint32_t)(v) >> 27) & 0x3U)
301+ static inline uint64_t dma_ccmd_sid (uint16_t sid )
302+ {
303+ return (((uint64_t )(sid & 0xffffU )) << 16U );
304+ }
305+
306+ static inline uint16_t dma_ccmd_did (uint16_t did )
307+ {
308+ return (did & 0xffffU );
309+ }
310+
311+ static inline uint8_t dma_ccmd_get_caig_32 (uint32_t gaig )
312+ {
313+ return ((gaig >> 27U ) & 0x3U );
314+ }
315+
293316
294317/* IOTLB_REG */
295318#define DMA_IOTLB_IVT (((uint64_t)1UL) << 63)
@@ -299,38 +322,118 @@ static inline uint8_t iommu_ecap_pds(uint64_t ecap)
299322#define DMA_IOTLB_PAGE_INVL (((uint64_t)3UL) << 60)
300323#define DMA_IOTLB_DR (((uint64_t)1UL) << 49)
301324#define DMA_IOTLB_DW (((uint64_t)1UL) << 48)
302- #define DMA_IOTLB_DID (d ) \
303- (((uint64_t)((d) & 0xffffUL)) << 32)
304- #define DMA_IOTLB_GET_IAIG_32 (v ) (((uint32_t)(v) >> 25) & 0x3U)
325+ static inline uint64_t dma_iotlb_did (uint16_t did )
326+ {
327+ return (((uint64_t )(did & 0xffffU )) << 32U );
328+ }
329+
330+ static inline uint8_t dma_iotlb_get_iaig_32 (uint32_t iai )
331+ {
332+ return ((iai >> 25U ) & 0x3U );
333+ }
305334
306335/* INVALIDATE_ADDRESS_REG */
307- #define DMA_IOTLB_INVL_ADDR_AM (m ) ((uint64_t)((m) & 0x3fUL))
336+ static inline uint8_t dma_iotlb_invl_addr_am (uint8_t am )
337+ {
338+ return (am & 0x3fU );
339+ }
340+
308341#define DMA_IOTLB_INVL_ADDR_IH_UNMODIFIED (((uint64_t)1UL) << 6)
309342
310343/* FECTL_REG */
311344#define DMA_FECTL_IM (((uint32_t)1U) << 31)
312345
313346/* FSTS_REG */
314- #define DMA_FSTS_PFO (s ) (((s) >> 0) & 1U)
315- #define DMA_FSTS_PPF (s ) (((s) >> 1) & 1U)
316- #define DMA_FSTS_AFO (s ) (((s) >> 2) & 1U)
317- #define DMA_FSTS_APF (s ) (((s) >> 3) & 1U)
318- #define DMA_FSTS_IQE (s ) (((s) >> 4) & 1U)
319- #define DMA_FSTS_ICE (s ) (((s) >> 5) & 1U)
320- #define DMA_FSTS_ITE (s ) (((s) >> 6) & 1U)
321- #define DMA_FSTS_PRO (s ) (((s) >> 7) & 1U)
322- #define DMA_FSTS_FRI (s ) (((s) >> 8) & 0xFFU)
347+ static inline bool dma_fsts_pfo (uint32_t PFO )
348+ {
349+ return ((PFO >> 0U ) & 1U ) == 1U ;
350+ }
351+
352+ static inline bool dma_fsts_ppf (uint32_t PPF )
353+ {
354+ return ((PPF >> 1U ) & 1U ) == 1U ;
355+ }
356+
357+ static inline bool dma_fsts_afo (uint32_t AFO )
358+ {
359+ return ((AFO >> 2U ) & 1U ) == 1U ;
360+ }
361+
362+ static inline bool dma_fsts_apf (uint32_t APF )
363+ {
364+ return ((APF >> 3U ) & 1U ) == 1U ;
365+ }
366+
367+ static inline bool dma_fsts_iqe (uint32_t IQE )
368+ {
369+ return ((IQE >> 4U ) & 1U ) == 1U ;
370+ }
371+
372+ static inline bool dma_fsts_ice (uint32_t ICE )
373+ {
374+ return ((ICE >> 5U ) & 1U ) == 1U ;
375+ }
376+
377+ static inline bool dma_fsts_ite (uint32_t ITE )
378+ {
379+ return ((ITE >> 6U ) & 1U ) == 1U ;
380+ }
381+
382+ static inline bool dma_fsts_pro (uint32_t PRO )
383+ {
384+ return ((PRO >> 7U ) & 1U ) == 1U ;
385+ }
386+
387+ static inline uint8_t dma_fsts_fri (uint32_t FRI )
388+ {
389+ return ((FRI >> 8U ) & 0xFFU );
390+ }
323391
324392/* FRCD_REGs: upper 64 bits*/
325- #define DMA_FRCD_UP_F (r ) (((r) >> 63) & 1UL)
326- #define DMA_FRCD_UP_T (r ) (((r) >> 62) & 1UL)
327- #define DMA_FRCD_UP_AT (r ) (((r) >> 60) & 3UL)
328- #define DMA_FRCD_UP_PASID (r ) (((r) >> 40) & 0xfffffUL)
329- #define DMA_FRCD_UP_FR (r ) (((r) >> 32) & 0xffUL)
330- #define DMA_FRCD_UP_PP (r ) (((r) >> 31) & 1UL)
331- #define DMA_FRCD_UP_EXE (r ) (((r) >> 30) & 1UL)
332- #define DMA_FRCD_UP_PRIV (r ) (((r) >> 29) & 1UL)
333- #define DMA_FRCD_UP_SID (r ) (((r) >> 0) & 0xffffUL)
393+ static inline bool dma_frcd_up_f (uint64_t UP_F )
394+ {
395+ return ((UP_F >> 63U ) & 1UL ) == 1UL ;
396+ }
397+
398+ static inline uint8_t dma_frcd_up_t (uint64_t UP_T )
399+ {
400+ return ((UP_T >> 62U ) & 1UL );
401+ }
402+
403+ static inline uint8_t dma_frcd_up_at (uint64_t UP_AT )
404+ {
405+ return ((UP_AT >> 60U ) & 3UL );
406+ }
407+
408+ static inline uint32_t dma_frcd_up_pasid (uint64_t UP_PASID )
409+ {
410+ return ((UP_PASID >> 40U ) & 0xfffffUL );
411+ }
412+
413+ static inline uint8_t dma_frcd_up_fr (uint64_t UP_FR )
414+ {
415+ return ((UP_FR >> 32U ) & 0xffUL );
416+ }
417+
418+ static inline bool dma_frcd_up_pp (uint64_t UP_PP )
419+ {
420+ return ((UP_PP >> 31U ) & 1UL ) == 1UL ;
421+ }
422+
423+ static inline bool dma_frcd_up_exe (uint64_t UP_EXE )
424+ {
425+ return ((UP_EXE >> 30U ) & 1UL ) == 1UL ;
426+ }
427+
428+ static inline bool dma_frcd_up_priv (uint64_t UP_PRIV )
429+ {
430+ return ((UP_PRIV >> 29U ) & 1UL ) == 1UL ;
431+ }
432+
433+ static inline uint32_t dma_frcd_up_sid (uint64_t UP_SID )
434+ {
435+ return ((UP_SID >> 0U ) & 0xffffUL );
436+ }
334437
335438#define DMAR_CONTEXT_TRANSLATION_TYPE_TRANSLATED 0x00U
336439#define DMAR_CONTEXT_TRANSLATION_TYPE_RESERVED 0x01U
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