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donshenglijinxia
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HV: Calling into VPCI init/unit functions for partition hypervisor
V4: - Clear address cache info after a full cf8/cfc access - Add NULL pointer checking when calling init/deinit ops V3: - Do not use ASSERT - Loop through the vdev list defined in vm_desctiption table to call the vdev init/unit functions - Make the cached vbdf info struct per vm instead of per pcpu V2: - Fixed MISRA violations Reviewed-by: Anthony Xu <anthony.xu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com> Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
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‎hypervisor/arch/x86/guest/vm.c

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@@ -186,6 +186,10 @@ int create_vm(struct vm_description *vm_desc, struct vm **rtn_vm)
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}
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vm->vpic = vpic_init(vm);
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#ifdef CONFIG_PARTITION_MODE
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vpci_init(vm);
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#endif
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/* vpic wire_mode default is INTR */
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vm->wire_mode = VPIC_WIRE_INTR;
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@@ -290,6 +294,10 @@ int shutdown_vm(struct vm *vm)
290294
vpic_cleanup(vm);
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}
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#ifdef CONFIG_PARTITION_MODE
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vpci_cleanup(vm);
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#endif
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free(vm->hw.vcpu_array);
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/* TODO: De-Configure HV-SW */

‎hypervisor/dm/vpci/pci_priv.h

Lines changed: 81 additions & 0 deletions
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@@ -0,0 +1,81 @@
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/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef PCI_PRIV_H_
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#define PCI_PRIV_H_
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#include <hv_debug.h>
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#include "vpci.h"
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#define PCIM_BAR_MEM_BASE 0xfffffff0U
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#define PCI_BAR_BASE(val) ((val) & PCIM_BAR_MEM_BASE)
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#define PCI_BAR(base, type) ((base) | (type))
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#define PCI_BUS(bdf) (((bdf) >> 8) & 0xFFU)
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#define PCI_SLOT(bdf) (((bdf) >> 3) & 0x1FU)
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#define PCI_FUNC(bdf) ((bdf) & 0x07U)
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#define LOBYTE(w) ((uint8_t)((w) & 0xffU))
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#define PCI_BUSMAX 0xffU
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#define PCI_SLOTMAX 0x1fU
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#define PCI_FUNCMAX 0x7U
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#define MAXBUSES (PCI_BUSMAX + 1U)
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#define MAXSLOTS (PCI_SLOTMAX + 1U)
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#define MAXFUNCS (PCI_FUNCMAX + 1U)
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#define PCIR_VENDOR 0x00U
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#define PCIR_DEVICE 0x02U
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#define PCIR_COMMAND 0x04U
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#define PCIM_CMD_MEMEN 0x0002U
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#define PCIR_REVID 0x08U
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#define PCIR_SUBCLASS 0x0aU
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#define PCIR_CLASS 0x0bU
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#define PCIR_HDRTYPE 0x0eU
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#define PCIM_HDRTYPE_NORMAL 0x00U
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#define PCIM_MFDEV 0x80U
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#define PCIR_BARS 0x10U
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#define PCIR_BAR(x) (PCIR_BARS + ((x) * 4U))
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#define PCIM_BAR_MEM_SPACE 0U
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#define PCIC_BRIDGE 0x06U
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#define PCIS_BRIDGE_HOST 0x00U
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#define PCI_CONFIG_ADDR 0xcf8U
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#define PCI_CONFIG_DATA 0xcfcU
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#define PCI_CFG_ENABLE 0x80000000U
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void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, uint16_t vbdf,
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uint32_t offset, uint32_t bytes, uint32_t *val);
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81+
#endif /* PCI_PRIV_H_ */

‎hypervisor/dm/vpci/vpci.c

Lines changed: 175 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,175 @@
1+
/*-
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* Copyright (c) 2011 NetApp, Inc.
3+
* Copyright (c) 2018 Intel Corporation
4+
* All rights reserved.
5+
*
6+
* Redistribution and use in source and binary forms, with or without
7+
* modification, are permitted provided that the following conditions
8+
* are met:
9+
* 1. Redistributions of source code must retain the above copyright
10+
* notice, this list of conditions and the following disclaimer.
11+
* 2. Redistributions in binary form must reproduce the above copyright
12+
* notice, this list of conditions and the following disclaimer in the
13+
* documentation and/or other materials provided with the distribution.
14+
*
15+
* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
16+
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17+
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18+
* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
19+
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20+
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21+
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22+
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23+
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
27+
* $FreeBSD$
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*/
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#include <hypervisor.h>
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#include <hv_lib.h>
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#include <acrn_common.h>
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#include <hv_arch.h>
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#include <hv_debug.h>
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#include "pci_priv.h"
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static bool is_cfg_addr(uint16_t addr)
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{
40+
return (addr >= PCI_CONFIG_ADDR) && (addr < (PCI_CONFIG_ADDR + 4));
41+
}
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static bool is_cfg_data(uint16_t addr)
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{
45+
return (addr >= PCI_CONFIG_DATA) && (addr < (PCI_CONFIG_DATA + 4));
46+
}
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static void pci_cfg_clear_cache(struct pci_addr_info *pi)
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{
50+
pi->cached_bdf = 0xffffU;
51+
pi->cached_reg = 0U;
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pi->cached_enable = 0U;
53+
}
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static uint32_t pci_cfg_io_read(__unused struct vm_io_handler *hdlr,
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struct vm *vm, uint16_t addr, size_t bytes)
57+
{
58+
uint32_t val = 0xffffffffU;
59+
struct vpci *vpci = &vm->vpci;
60+
struct pci_addr_info *pi = &vpci->addr_info;
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if (is_cfg_addr(addr)) {
63+
/* TODO: handling the non 4 bytes access */
64+
if (bytes == 4U) {
65+
val = (PCI_BUS(pi->cached_bdf) << 16)
66+
| (PCI_SLOT(pi->cached_bdf) << 11)
67+
| (PCI_FUNC(pi->cached_bdf) << 8)
68+
| pi->cached_reg;
69+
70+
if (pi->cached_enable) {
71+
val |= PCI_CFG_ENABLE;
72+
}
73+
}
74+
} else if (is_cfg_data(addr)) {
75+
if (pi->cached_enable) {
76+
uint16_t offset = addr - 0xcfc;
77+
78+
pci_vdev_cfg_handler(&vm->vpci, 1U, pi->cached_bdf,
79+
pi->cached_reg + offset, bytes, &val);
80+
81+
pci_cfg_clear_cache(pi);
82+
}
83+
} else {
84+
val = 0xffffffffU;
85+
}
86+
87+
return val;
88+
}
89+
90+
static void pci_cfg_io_write(__unused struct vm_io_handler *hdlr,
91+
struct vm *vm, uint16_t addr, size_t bytes, uint32_t val)
92+
{
93+
struct vpci *vpci = &vm->vpci;
94+
struct pci_addr_info *pi = &vpci->addr_info;
95+
96+
if (is_cfg_addr(addr)) {
97+
/* TODO: handling the non 4 bytes access */
98+
if (bytes == 4U) {
99+
pi->cached_bdf = PCI_BDF(
100+
((val >> 16) & PCI_BUSMAX),
101+
((val >> 11) & PCI_SLOTMAX),
102+
((val >> 8) & PCI_FUNCMAX));
103+
104+
pi->cached_reg = val & PCI_REGMAX;
105+
pi->cached_enable =
106+
(val & PCI_CFG_ENABLE) == PCI_CFG_ENABLE;
107+
}
108+
} else if (is_cfg_data(addr)) {
109+
if (pi->cached_enable) {
110+
uint16_t offset = addr - 0xcfc;
111+
112+
pci_vdev_cfg_handler(&vm->vpci, 0U, pi->cached_bdf,
113+
pi->cached_reg + offset, bytes, &val);
114+
115+
pci_cfg_clear_cache(pi);
116+
}
117+
} else {
118+
pr_err("Not PCI cfg data/addr port access!");
119+
}
120+
121+
}
122+
123+
void vpci_init(struct vm *vm)
124+
{
125+
struct vpci *vpci = &vm->vpci;
126+
struct vpci_vdev_array *vdev_array;
127+
struct pci_vdev *vdev;
128+
int i;
129+
int ret;
130+
struct vm_io_range pci_cfg_range = {.flags = IO_ATTR_RW,
131+
.base = PCI_CONFIG_ADDR, .len = 8U};
132+
133+
vpci->vm = vm;
134+
vdev_array = vm->vm_desc->vpci_vdev_array;
135+
136+
for (i = 0; i < vdev_array->num_pci_vdev; i++) {
137+
vdev = &vdev_array->vpci_vdev_list[i];
138+
vdev->vpci = vpci;
139+
if ((vdev->ops != NULL) && (vdev->ops->init != NULL)) {
140+
ret = vdev->ops->init(vdev);
141+
if (ret) {
142+
pr_err("vdev->ops->init failed!");
143+
}
144+
}
145+
}
146+
147+
register_io_emulation_handler(vm, &pci_cfg_range,
148+
&pci_cfg_io_read, &pci_cfg_io_write);
149+
}
150+
151+
void vpci_cleanup(struct vm *vm)
152+
{
153+
struct vpci_vdev_array *vdev_array;
154+
struct pci_vdev *vdev;
155+
int i;
156+
int ret;
157+
158+
vdev_array = vm->vm_desc->vpci_vdev_array;
159+
160+
for (i = 0; i < vdev_array->num_pci_vdev; i++) {
161+
vdev = &vdev_array->vpci_vdev_list[i];
162+
if ((vdev->ops != NULL) && (vdev->ops->deinit != NULL)) {
163+
ret = vdev->ops->deinit(vdev);
164+
if (ret) {
165+
pr_err("vdev->ops->deinit failed!");
166+
}
167+
}
168+
}
169+
}
170+
171+
void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, uint16_t vbdf,
172+
uint32_t offset, uint32_t bytes, uint32_t *val)
173+
{
174+
/* vm-exit handler */
175+
}

‎hypervisor/include/dm/vpci/vpci.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,4 +92,7 @@ struct vpci {
9292
struct pci_addr_info addr_info;
9393
};
9494

95+
void vpci_init(struct vm *vm);
96+
void vpci_cleanup(struct vm *vm);
97+
9598
#endif /* VPCI_H_ */

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