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Wei LiuNanlinXie
Wei Liu
authored and
NanlinXie
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hv: add suffix(U/UL) to come up MISRA-C into include
MISRA-C required the suffix(U/UL), such as: (1) ---> (1U) (1) ---> (1UL) (1U << 0) ---> (1U << 0U) This patch will add the suffix(U/UL) to come up MISRA-C into hypervisor/include directory. Tracked-On: #1468 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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12 files changed

+49
-49
lines changed

12 files changed

+49
-49
lines changed

‎hypervisor/arch/x86/guest/vcpu.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -287,8 +287,8 @@ void set_ap_entry(struct vcpu *vcpu, uint64_t entry)
287287
struct ext_context *ectx;
288288

289289
ectx = &(vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context].ext_ctx);
290-
ectx->cs.selector = (uint16_t)((entry >> 4UL) & 0xFFFFU);
291-
ectx->cs.base = ectx->cs.selector << 4UL;
290+
ectx->cs.selector = (uint16_t)((entry >> 4U) & 0xFFFFU);
291+
ectx->cs.base = ectx->cs.selector << 4U;
292292

293293
vcpu_set_rip(vcpu, 0UL);
294294
}

‎hypervisor/arch/x86/guest/vlapic.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -46,9 +46,9 @@ static inline uint32_t prio(uint32_t x)
4646
#define VLAPIC_VERSION (16U)
4747

4848
#define APICBASE_RESERVED 0x000002ffU
49-
#define APICBASE_BSP 0x00000100U
49+
#define APICBASE_BSP 0x00000100UL
5050
#define APICBASE_X2APIC 0x00000400U
51-
#define APICBASE_ENABLED 0x00000800U
51+
#define APICBASE_ENABLED 0x00000800UL
5252

5353
#define ACRN_DBG_LAPIC 6U
5454

@@ -1748,7 +1748,7 @@ vlapic_enabled(struct acrn_vlapic *vlapic)
17481748
{
17491749
struct lapic_regs *lapic = &(vlapic->apic_page);
17501750

1751-
if (((vlapic->msr_apicbase & APICBASE_ENABLED) != 0U) &&
1751+
if (((vlapic->msr_apicbase & APICBASE_ENABLED) != 0UL) &&
17521752
((lapic->svr.v & APIC_SVR_ENABLE) != 0U)) {
17531753
return true;
17541754
} else {

‎hypervisor/include/arch/x86/apicreg.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -182,7 +182,7 @@ union ioapic_rte {
182182
*/
183183

184184
/* default physical locations of LOCAL (CPU) APICs */
185-
#define DEFAULT_APIC_BASE 0xfee00000U
185+
#define DEFAULT_APIC_BASE 0xfee00000UL
186186

187187
/* constants relating to APIC ID registers */
188188
#define APIC_ID_MASK 0xff000000U

‎hypervisor/include/arch/x86/cpu.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -39,15 +39,15 @@
3939
#define CPU_H
4040

4141
/* Define page size */
42-
#define CPU_PAGE_SHIFT 12
42+
#define CPU_PAGE_SHIFT 12U
4343
#define CPU_PAGE_SIZE 0x1000U
4444
#define CPU_PAGE_MASK 0xFFFFFFFFFFFFF000UL
4545

4646
/* Assume the max physcial cpu number is 128 */
4747
#define MAX_PCPU_NUM 128U
4848

4949
#define MMU_PTE_PAGE_SHIFT CPU_PAGE_SHIFT
50-
#define MMU_PDE_PAGE_SHIFT 21
50+
#define MMU_PDE_PAGE_SHIFT 21U
5151

5252
/* Define CPU stack alignment */
5353
#define CPU_STACK_ALIGN 16UL
@@ -269,7 +269,7 @@ extern spinlock_t trampoline_spinlock;
269269

270270
/* CPU states defined */
271271
enum pcpu_boot_state {
272-
PCPU_STATE_RESET = 0,
272+
PCPU_STATE_RESET = 0U,
273273
PCPU_STATE_INITIALIZING,
274274
PCPU_STATE_RUNNING,
275275
PCPU_STATE_HALTED,
@@ -518,7 +518,7 @@ write_xcr(int reg, uint64_t val)
518518
uint32_t low, high;
519519

520520
low = (uint32_t)val;
521-
high = (uint32_t)(val >> 32);
521+
high = (uint32_t)(val >> 32U);
522522
asm volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
523523
}
524524
#else /* ASSEMBLER defined */

‎hypervisor/include/arch/x86/irq.h

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -92,17 +92,17 @@ uint32_t irq_to_vector(uint32_t irq);
9292
/*
9393
* Some MSI message definitions
9494
*/
95-
#define MSI_ADDR_MASK 0xfff00000U
96-
#define MSI_ADDR_BASE 0xfee00000U
97-
#define MSI_ADDR_RH 0x00000008U /* Redirection Hint */
98-
#define MSI_ADDR_LOG 0x00000004U /* Destination Mode */
95+
#define MSI_ADDR_MASK 0xfff00000UL
96+
#define MSI_ADDR_BASE 0xfee00000UL
97+
#define MSI_ADDR_RH 0x00000008UL /* Redirection Hint */
98+
#define MSI_ADDR_LOG 0x00000004UL /* Destination Mode */
9999

100100
/* RFLAGS */
101-
#define HV_ARCH_VCPU_RFLAGS_IF (1U<<9)
101+
#define HV_ARCH_VCPU_RFLAGS_IF (1UL<<9U)
102102

103103
/* Interruptability State info */
104-
#define HV_ARCH_VCPU_BLOCKED_BY_MOVSS (1U<<1)
105-
#define HV_ARCH_VCPU_BLOCKED_BY_STI (1U<<0)
104+
#define HV_ARCH_VCPU_BLOCKED_BY_MOVSS (1UL<<1U)
105+
#define HV_ARCH_VCPU_BLOCKED_BY_STI (1UL<<0U)
106106

107107
void vcpu_inject_extint(struct vcpu *vcpu);
108108
void vcpu_inject_nmi(struct vcpu *vcpu);

‎hypervisor/include/arch/x86/lapic.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -86,11 +86,11 @@
8686
#define LAPIC_DIVIDE_CONFIGURATION_REGISTER 0x000003E0U
8787

8888
/* LAPIC CPUID bit and bitmask definitions */
89-
#define CPUID_OUT_RDX_APIC_PRESENT ((uint64_t) 1UL << 9)
90-
#define CPUID_OUT_RCX_X2APIC_PRESENT ((uint64_t) 1UL << 21)
89+
#define CPUID_OUT_RDX_APIC_PRESENT ((uint64_t) 1UL << 9U)
90+
#define CPUID_OUT_RCX_X2APIC_PRESENT ((uint64_t) 1UL << 21U)
9191

9292
/* LAPIC MSR bit and bitmask definitions */
93-
#define MSR_01B_XAPIC_GLOBAL_ENABLE ((uint64_t) 1UL << 11)
93+
#define MSR_01B_XAPIC_GLOBAL_ENABLE ((uint64_t) 1UL << 11U)
9494

9595
/* LAPIC register bit and bitmask definitions */
9696
#define LAPIC_SVR_VECTOR 0x000000FFU
@@ -100,9 +100,9 @@
100100
#define LAPIC_DELIVERY_MODE_EXTINT_MASK 0x00000700U
101101

102102
/* LAPIC Timer bit and bitmask definitions */
103-
#define LAPIC_TMR_ONESHOT ((uint32_t) 0x0U << 17)
104-
#define LAPIC_TMR_PERIODIC ((uint32_t) 0x1U << 17)
105-
#define LAPIC_TMR_TSC_DEADLINE ((uint32_t) 0x2U << 17)
103+
#define LAPIC_TMR_ONESHOT ((uint32_t) 0x0U << 17U)
104+
#define LAPIC_TMR_PERIODIC ((uint32_t) 0x1U << 17U)
105+
#define LAPIC_TMR_TSC_DEADLINE ((uint32_t) 0x2U << 17U)
106106

107107
enum intr_cpu_startup_shorthand {
108108
INTR_CPU_STARTUP_USE_DEST,

‎hypervisor/include/arch/x86/msr.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -498,9 +498,9 @@
498498
#define MSR_IA32_EFER_NXE_BIT (1UL<<11U)
499499

500500
/* FEATURE CONTROL bits */
501-
#define MSR_IA32_FEATURE_CONTROL_LOCK (1U<<0)
502-
#define MSR_IA32_FEATURE_CONTROL_VMX_SMX (1U<<1)
503-
#define MSR_IA32_FEATURE_CONTROL_VMX_NO_SMX (1U<<2)
501+
#define MSR_IA32_FEATURE_CONTROL_LOCK (1U<<0U)
502+
#define MSR_IA32_FEATURE_CONTROL_VMX_SMX (1U<<1U)
503+
#define MSR_IA32_FEATURE_CONTROL_VMX_NO_SMX (1U<<2U)
504504

505505
/* PAT memory type definitions */
506506
#define PAT_MEM_TYPE_UC 0x00UL /* uncached */
@@ -553,8 +553,8 @@ static inline bool pat_mem_type_invalid(uint64_t x)
553553
#define MTRR_VALID 0x800U /* MTRR setting is valid */
554554

555555
/* SPEC & PRED bit */
556-
#define SPEC_ENABLE_IBRS (1U<<0)
557-
#define SPEC_ENABLE_STIBP (1U<<1)
558-
#define PRED_SET_IBPB (1U<<0)
556+
#define SPEC_ENABLE_IBRS (1U<<0U)
557+
#define SPEC_ENABLE_STIBP (1U<<1U)
558+
#define PRED_SET_IBPB (1U<<0U)
559559

560560
#endif /* MSR_H */

‎hypervisor/include/arch/x86/mtrr.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
#define MTRR_H
88

99
#define FIXED_RANGE_MTRR_NUM 11U
10-
#define MTRR_SUB_RANGE_NUM 8U
10+
#define MTRR_SUB_RANGE_NUM 8U
1111

1212
union mtrr_cap_reg {
1313
uint64_t value;

‎hypervisor/include/arch/x86/trusty.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,9 +7,9 @@
77
#ifndef TRUSTY_H_
88
#define TRUSTY_H_
99

10-
#define BOOTLOADER_SEED_MAX_ENTRIES 10U
11-
#define RPMB_MAX_PARTITION_NUMBER 6
12-
#define MMC_PROD_NAME_WITH_PSN_LEN 15
10+
#define BOOTLOADER_SEED_MAX_ENTRIES 10U
11+
#define RPMB_MAX_PARTITION_NUMBER 6U
12+
#define MMC_PROD_NAME_WITH_PSN_LEN 15U
1313
#define BUP_MKHI_BOOTLOADER_SEED_LEN 64U
1414

1515
/* Trusty EPT rebase gpa: 511G */

‎hypervisor/include/arch/x86/vtd.h

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -315,13 +315,13 @@ static inline uint8_t dma_ccmd_get_caig_32(uint32_t gaig)
315315

316316

317317
/* IOTLB_REG */
318-
#define DMA_IOTLB_IVT (((uint64_t)1UL) << 63)
319-
#define DMA_IOTLB_IVT_32 (((uint32_t)1U) << 31)
320-
#define DMA_IOTLB_GLOBAL_INVL (((uint64_t)1UL) << 60)
321-
#define DMA_IOTLB_DOMAIN_INVL (((uint64_t)2UL) << 60)
322-
#define DMA_IOTLB_PAGE_INVL (((uint64_t)3UL) << 60)
323-
#define DMA_IOTLB_DR (((uint64_t)1UL) << 49)
324-
#define DMA_IOTLB_DW (((uint64_t)1UL) << 48)
318+
#define DMA_IOTLB_IVT (((uint64_t)1UL) << 63U)
319+
#define DMA_IOTLB_IVT_32 (((uint32_t)1U) << 31U)
320+
#define DMA_IOTLB_GLOBAL_INVL (((uint64_t)1UL) << 60U)
321+
#define DMA_IOTLB_DOMAIN_INVL (((uint64_t)2UL) << 60U)
322+
#define DMA_IOTLB_PAGE_INVL (((uint64_t)3UL) << 60U)
323+
#define DMA_IOTLB_DR (((uint64_t)1UL) << 49U)
324+
#define DMA_IOTLB_DW (((uint64_t)1UL) << 48U)
325325
static inline uint64_t dma_iotlb_did(uint16_t did)
326326
{
327327
return (((uint64_t)(did & 0xffffU)) << 32U);
@@ -338,10 +338,10 @@ static inline uint8_t dma_iotlb_invl_addr_am(uint8_t am)
338338
return (am & 0x3fU);
339339
}
340340

341-
#define DMA_IOTLB_INVL_ADDR_IH_UNMODIFIED (((uint64_t)1UL) << 6)
341+
#define DMA_IOTLB_INVL_ADDR_IH_UNMODIFIED (((uint64_t)1UL) << 6U)
342342

343343
/* FECTL_REG */
344-
#define DMA_FECTL_IM (((uint32_t)1U) << 31)
344+
#define DMA_FECTL_IM (((uint32_t)1U) << 31U)
345345

346346
/* FSTS_REG */
347347
static inline bool dma_fsts_pfo(uint32_t pfo)
@@ -441,7 +441,7 @@ static inline uint32_t dma_frcd_up_sid(uint64_t up_sid)
441441

442442
#define DRHD_FLAG_INCLUDE_PCI_ALL_MASK (1U)
443443

444-
#define DEVFUN(dev, fun) (((dev & 0x1FU) << 3) | ((fun & 0x7U)))
444+
#define DEVFUN(dev, fun) (((dev & 0x1FU) << 3U) | ((fun & 0x7U)))
445445

446446
struct dmar_dev_scope {
447447
uint8_t bus;

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