HV:guest:add suffix U to the numeric constant

Add suffix U to the numeric constant

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

Author: Shawnshh

hypervisor/arch/x86/guest/instr_emul.c

@@ -691,7 +691,7 @@ emulate_movs(struct vcpu *vcpu, __unused uint64_t gpa, struct vie *vie,
 		 * The count register is %rcx, %ecx or %cx depending on the
 		 * address size of the instruction.
 		 */
-		if ((rcx & vie_size2mask(vie->addrsize)) == 0) {
+		if ((rcx & vie_size2mask(vie->addrsize)) == 0UL) {
 			error = 0;
 			goto done;
 		}
@@ -745,7 +745,7 @@ emulate_movs(struct vcpu *vcpu, __unused uint64_t gpa, struct vie *vie,
 		/*
 		 * Repeat the instruction if the count register is not zero.
 		 */
-		if ((rcx & vie_size2mask(vie->addrsize)) != 0)
+		if ((rcx & vie_size2mask(vie->addrsize)) != 0UL)
 			VCPU_RETAIN_RIP(vcpu);
 	}
 done:
@@ -763,7 +763,7 @@ emulate_stos(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 	uint64_t val;
 	uint64_t rcx, rdi, rflags;
 
-	opsize = (vie->op.op_byte == 0xAA) ? 1 : vie->opsize;
+	opsize = (vie->op.op_byte == 0xAAU) ? 1 : vie->opsize;
 	repeat = vie->repz_present | vie->repnz_present;
 
 	if (repeat != 0) {

hypervisor/arch/x86/guest/vioapic.c

@@ -244,9 +244,9 @@ vioapic_read(struct vioapic *vioapic, uint32_t addr)
 	    (regnum < IOAPIC_REDTBL + vioapic_pincount(vioapic->vm) * 2) != 0) {
 		pin = (regnum - IOAPIC_REDTBL) / 2;
 		if (((regnum - IOAPIC_REDTBL) % 2) != 0)
-			rshift = 32;
+			rshift = 32U;
 		else
-			rshift = 0;
+			rshift = 0U;
 
 		return vioapic->rtbl[pin].reg >> rshift;
 	}
@@ -427,7 +427,7 @@ vioapic_mmio_rw(struct vioapic *vioapic, uint64_t gpa,
 	if (size != 4 || (offset != IOREGSEL && offset != IOWIN &&
 			offset != IOEOI)) {
 		if (doread)
-			*data = 0;
+			*data = 0UL;
 		return 0;
 	}
 
@@ -581,7 +581,7 @@ int vioapic_mmio_access_handler(struct vcpu *vcpu, struct mem_io *mmio,
 	int ret = 0;
 
 	/* Note all RW to IOAPIC are 32-Bit in size */
-	ASSERT(mmio->access_size == 4,
+	ASSERT(mmio->access_size == 4U,
 			"All RW to LAPIC must be 32-bits in size");
 
 	if (mmio->read_write == HV_MEM_IO_READ) {
@@ -637,7 +637,7 @@ void get_vioapic_info(char *str, int str_max, int vmid)
 	size -= len;
 	str += len;
 
-	rte = 0;
+	rte = 0UL;
 	for (pin = 0 ; pin < vioapic_pincount(vm); pin++) {
 		vioapic_get_rte(vm, pin, (void *)&rte);
 		low = rte;

hypervisor/arch/x86/guest/vlapic.c

@@ -279,8 +279,8 @@ static void vlapic_reset_timer(struct vlapic *vlapic)
 	timer = &vlapic->vlapic_timer.timer;
 	del_timer(timer);
 	timer->mode = 0;
-	timer->fire_tsc = 0;
-	timer->period_in_cycle = 0;
+	timer->fire_tsc = 0UL;
+	timer->period_in_cycle = 0UL;
 }
 
 static bool
@@ -296,7 +296,7 @@ set_expiration(struct vlapic *vlapic)
 	tmicr = vlapic_timer->tmicr;
 	divisor_shift = vlapic_timer->divisor_shift;
 
-	if (!tmicr || divisor_shift > 8)
+	if (!tmicr || divisor_shift > 8U)
 		return false;
 
 	delta = tmicr << divisor_shift;
@@ -325,8 +325,8 @@ static void vlapic_update_lvtt(struct vlapic *vlapic,
 		del_timer(timer);
 		timer->mode = (timer_mode == APIC_LVTT_TM_PERIODIC) ?
 				TICK_MODE_PERIODIC: TICK_MODE_ONESHOT;
-		timer->fire_tsc = 0;
-		timer->period_in_cycle = 0;
+		timer->fire_tsc = 0UL;
+		timer->period_in_cycle = 0UL;
 
 		vlapic_timer->mode = timer_mode;
 	}
@@ -385,7 +385,7 @@ static uint64_t vlapic_get_tsc_deadline_msr(struct vlapic *vlapic)
 	if (!vlapic_lvtt_tsc_deadline(vlapic))
 		return 0;
 
-	return (vlapic->vlapic_timer.timer.fire_tsc == 0) ? 0 :
+	return (vlapic->vlapic_timer.timer.fire_tsc == 0UL) ? 0UL :
 			vlapic->vcpu->guest_msrs[IDX_TSC_DEADLINE];
 
 }
@@ -412,7 +412,7 @@ static void vlapic_set_tsc_deadline_msr(struct vlapic *vlapic,
 
 		add_timer(timer);
 	} else
-		timer->fire_tsc = 0;
+		timer->fire_tsc = 0UL;
 }
 
 static void
@@ -422,7 +422,7 @@ vlapic_esr_write_handler(struct vlapic *vlapic)
 
 	lapic = vlapic->apic_page;
 	lapic->esr = vlapic->esr_pending;
-	vlapic->esr_pending = 0;
+	vlapic->esr_pending = 0U;
 }
 
 /*
@@ -652,7 +652,7 @@ vlapic_fire_lvt(struct vlapic *vlapic, uint32_t lvt)
 
 	switch (mode) {
 	case APIC_LVT_DM_FIXED:
-		if (vec < 16) {
+		if (vec < 16U) {
 			vlapic_set_error(vlapic, APIC_ESR_SEND_ILLEGAL_VECTOR);
 			return 0;
 		}
@@ -876,7 +876,7 @@ vlapic_calcdest(struct vm *vm, uint64_t *dmask, uint32_t dest,
 	uint64_t amask;
 	uint16_t vcpu_id;
 
-	if (dest == 0xff) {
+	if (dest == 0xffU) {
 		/*
 		 * Broadcast in both logical and physical modes.
 		 */
@@ -888,7 +888,7 @@ vlapic_calcdest(struct vm *vm, uint64_t *dmask, uint32_t dest,
 		/*
 		 * Physical mode: destination is LAPIC ID.
 		 */
-		*dmask = 0;
+		*dmask = 0UL;
 		vcpu_id = vm_apicid2vcpu_id(vm, dest);
 		if (vcpu_id < phys_cpu_num)
 			bitmap_set(vcpu_id, dmask);
@@ -910,7 +910,7 @@ vlapic_calcdest(struct vm *vm, uint64_t *dmask, uint32_t dest,
 		 * Logical mode: match each APIC that has a bit set
 		 * in its LDR that matches a bit in the ldest.
 		 */
-		*dmask = 0;
+		*dmask = 0UL;
 		amask = vm_active_cpus(vm);
 		while ((vcpu_id = ffs64(amask)) != INVALID_BIT_INDEX) {
 			bitmap_clear(vcpu_id, &amask);
@@ -995,7 +995,7 @@ vlapic_set_cr8(struct vlapic *vlapic, uint64_t val)
 	uint8_t tpr;
 
 	if ((val & ~0xfUL) != 0U) {
-		vcpu_inject_gp(vlapic->vcpu, 0);
+		vcpu_inject_gp(vlapic->vcpu, 0U);
 		return;
 	}
 
@@ -1030,10 +1030,10 @@ vlapic_icrlo_write_handler(struct vlapic *vlapic)
 	dest = icrval >> (32 + 24);
 	vec = icrval & APIC_VECTOR_MASK;
 	mode = icrval & APIC_DELMODE_MASK;
-	phys = ((icrval & APIC_DESTMODE_LOG) == 0);
+	phys = ((icrval & APIC_DESTMODE_LOG) == 0UL);
 	shorthand = icrval & APIC_DEST_MASK;
 
-	if (mode == APIC_DELMODE_FIXED && vec < 16) {
+	if (mode == APIC_DELMODE_FIXED && vec < 16U) {
 		vlapic_set_error(vlapic, APIC_ESR_SEND_ILLEGAL_VECTOR);
 		dev_dbg(ACRN_DBG_LAPIC, "Ignoring invalid IPI %d", vec);
 		return 0;
@@ -1248,12 +1248,12 @@ vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
 		dev_dbg(ACRN_DBG_LAPIC,
 			"x2APIC MSR read from offset %#lx in xAPIC mode",
 			offset);
-		*data = 0;
+		*data = 0UL;
 		goto done;
 	}
 
 	if (offset > sizeof(*lapic)) {
-		*data = 0;
+		*data = 0UL;
 		goto done;
 	}
 
@@ -1346,7 +1346,7 @@ vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
 	case APIC_OFFSET_TIMER_ICR:
 		/* if TSCDEADLINE mode always return 0*/
 		if (vlapic_lvtt_tsc_deadline(vlapic))
-			*data = 0;
+			*data = 0UL;
 		else
 			*data = lapic->icr_timer;
 		break;
@@ -1360,11 +1360,11 @@ vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
 		/*
 		 * XXX generate a GP fault if vlapic is in x2apic mode
 		 */
-		*data = 0;
+		*data = 0UL;
 		break;
 	case APIC_OFFSET_RRR:
 	default:
-		*data = 0;
+		*data = 0UL;
 		break;
 	}
 done:

hypervisor/arch/x86/guest/vmsr.c

@@ -57,10 +57,10 @@ void disable_msr_interception(uint8_t *bitmap, uint32_t msr)
 	uint8_t *write_map;
 	uint8_t value;
 	/* low MSR */
-	if (msr < 0x1FFF) {
+	if (msr < 0x1FFFU) {
 		read_map = bitmap;
 		write_map = bitmap + 2048;
-	} else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
+	} else if ((msr >= 0xc0000000U) && (msr <= 0xc0001fffU)) {
 		read_map = bitmap + 1024;
 		write_map = bitmap + 3072;
 	} else {
@@ -177,7 +177,7 @@ int rdmsr_vmexit_handler(struct vcpu *vcpu)
 #ifdef CONFIG_MTRR_ENABLED
 		v = mtrr_rdmsr(vcpu, msr);
 #else
-		vcpu_inject_gp(vcpu, 0);
+		vcpu_inject_gp(vcpu, 0U);
 #endif
 		break;
 	}
@@ -232,7 +232,7 @@ int rdmsr_vmexit_handler(struct vcpu *vcpu)
 			msr <= MSR_IA32_VMX_TRUE_ENTRY_CTLS))) {
 			pr_warn("rdmsr: %lx should not come here!", msr);
 		}
-		vcpu_inject_gp(vcpu, 0);
+		vcpu_inject_gp(vcpu, 0U);
 		v = 0UL;
 		break;
 	}
@@ -293,13 +293,13 @@ int wrmsr_vmexit_handler(struct vcpu *vcpu)
 #ifdef CONFIG_MTRR_ENABLED
 		mtrr_wrmsr(vcpu, msr, v);
 #else
-		vcpu_inject_gp(vcpu, 0);
+		vcpu_inject_gp(vcpu, 0U);
 #endif
 		break;
 	}
 	case MSR_IA32_MTRR_CAP:
 	{
-		vcpu_inject_gp(vcpu, 0);
+		vcpu_inject_gp(vcpu, 0U);
 		break;
 	}
 	case MSR_IA32_BIOS_SIGN_ID:
@@ -366,7 +366,7 @@ int wrmsr_vmexit_handler(struct vcpu *vcpu)
 			msr <= MSR_IA32_VMX_TRUE_ENTRY_CTLS))) {
 			pr_warn("rdmsr: %lx should not come here!", msr);
 		}
-		vcpu_inject_gp(vcpu, 0);
+		vcpu_inject_gp(vcpu, 0U);
 		break;
 	}
 	}