HV: treewide: unify the type of bit-field members

Qualified or unqualified int or bool are the only types allowed for bit-field
members in C99, and MISRA C further forbids using plain int.

Use uint32_t (which is equivalent to unsigned int) for all bit-field members.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

Author: junjiemao1

hypervisor/arch/x86/lapic.c

@@ -20,26 +20,26 @@ union apic_icr {
 		uint32_t hi_32;
 	} value_32;
 	struct {
-		uint64_t vector:8;
-		uint64_t delivery_mode:3;
-		uint64_t destination_mode:1;
-		uint64_t delivery_status:1;
-		uint64_t rsvd_1:1;
-		uint64_t level:1;
-		uint64_t trigger_mode:1;
-		uint64_t rsvd_2:2;
-		uint64_t shorthand:2;
-		uint64_t rsvd_3:12;
-		uint64_t rsvd_4:32;
+		uint32_t vector:8;
+		uint32_t delivery_mode:3;
+		uint32_t destination_mode:1;
+		uint32_t delivery_status:1;
+		uint32_t rsvd_1:1;
+		uint32_t level:1;
+		uint32_t trigger_mode:1;
+		uint32_t rsvd_2:2;
+		uint32_t shorthand:2;
+		uint32_t rsvd_3:12;
+		uint32_t rsvd_4:32;
 	} bits;
 	struct {
-		uint64_t rsvd_1:32;
-		uint64_t rsvd_2:24;
-		uint64_t dest_field:8;
+		uint32_t rsvd_1:32;
+		uint32_t rsvd_2:24;
+		uint32_t dest_field:8;
 	} x_bits;
 	struct {
-		uint64_t rsvd_1:32;
-		uint64_t dest_field:32;
+		uint32_t rsvd_1:32;
+		uint32_t dest_field:32;
 	} x2_bits;
 };
 
@@ -116,13 +116,13 @@ union apic_lvt {
 union lapic_base_msr {
 	uint64_t value;
 	struct {
-		uint64_t rsvd_1:8;
-		uint64_t bsp:1;
-		uint64_t rsvd_2:1;
-		uint64_t x2APIC_enable:1;
-		uint64_t xAPIC_enable:1;
-		uint64_t lapic_paddr:24;
-		uint64_t rsvd_3:28;
+		uint32_t rsvd_1:8;
+		uint32_t bsp:1;
+		uint32_t rsvd_2:1;
+		uint32_t x2APIC_enable:1;
+		uint32_t xAPIC_enable:1;
+		uint32_t lapic_paddr:24;
+		uint32_t rsvd_3:28;
 	} fields;
 };
 

hypervisor/arch/x86/mmu.c

@@ -74,10 +74,11 @@ static inline void _invvpid(uint64_t type, uint16_t vpid, uint64_t gva)
 	int error = 0;
 
 	struct {
-		uint64_t vpid : 16;
-		uint64_t rsvd : 48;
+		uint32_t vpid : 16;
+		uint32_t rsvd1 : 16;
+		uint32_t rsvd2 : 32;
 		uint64_t gva;
-	} operand = { vpid, 0, gva };
+	} operand = { vpid, 0U, 0U, gva };
 
 	asm volatile ("invvpid %1, %2\n"
 			VMFAIL_INVALID_EPT_VPID

hypervisor/include/arch/x86/apicreg.h

@@ -121,8 +121,8 @@
 
 #ifndef LOCORE
 
-#define PAD3	int: 32; int: 32; int: 32
-#define PAD4	int: 32; int: 32; int: 32; int: 32
+#define PAD3	uint32_t: 32; uint32_t: 32; uint32_t: 32
+#define PAD4	uint32_t: 32; uint32_t: 32; uint32_t: 32; uint32_t: 32
 
 struct lapic_reg {
 	uint32_t val;		PAD3;

hypervisor/include/arch/x86/mtrr.h

@@ -12,24 +12,24 @@
 union mtrr_cap_reg {
 	uint64_t value;
 	struct {
-		uint64_t vcnt:8;
-		uint64_t fix:1;
-		uint64_t res0:1;
-		uint64_t wc:1;
-		uint64_t res1:21;
-		uint64_t res2:32;
+		uint32_t vcnt:8;
+		uint32_t fix:1;
+		uint32_t res0:1;
+		uint32_t wc:1;
+		uint32_t res1:21;
+		uint32_t res2:32;
 	} bits;
 };
 
 union mtrr_def_type_reg {
 	uint64_t value;
 	struct {
-		uint64_t type:8;
-		uint64_t res0:2;
-		uint64_t fixed_enable:1;
-		uint64_t enable:1;
-		uint64_t res1:20;
-		uint64_t res2:32;
+		uint32_t type:8;
+		uint32_t res0:2;
+		uint32_t fixed_enable:1;
+		uint32_t enable:1;
+		uint32_t res1:20;
+		uint32_t res2:32;
 	} bits;
 };