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zhenggenjren1
zhenggen
authored and
jren1
committed
MMU: bug fix on operating va <=> pa convertion
Before referencing to physical address of devs such as lapic, ioapic, vtd, and uart, switch to virtual address. Use a phisical address of pml4 to write CR3. Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
1 parent d02f4d4 commit c5f860e

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7 files changed

+37
-37
lines changed

7 files changed

+37
-37
lines changed

‎hypervisor/arch/x86/interrupt.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -215,11 +215,11 @@ void dump_lapic(void)
215215
{
216216
dev_dbg(ACRN_DBG_INTR,
217217
"LAPIC: TIME %08x, init=0x%x cur=0x%x ISR=0x%x IRR=0x%x",
218-
mmio_read_long((void*)(0xFEE00000 + LAPIC_LVT_TIMER_REGISTER)),
219-
mmio_read_long((void*)(0xFEE00000 + LAPIC_INITIAL_COUNT_REGISTER)),
220-
mmio_read_long((void*)(0xFEE00000 + LAPIC_CURRENT_COUNT_REGISTER)),
221-
mmio_read_long((void*)(0xFEE00000 + LAPIC_IN_SERVICE_REGISTER_7)),
222-
mmio_read_long((void*)(0xFEE00000 + LAPIC_INT_REQUEST_REGISTER_7)));
218+
mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_LVT_TIMER_REGISTER)),
219+
mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_INITIAL_COUNT_REGISTER)),
220+
mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_CURRENT_COUNT_REGISTER)),
221+
mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_IN_SERVICE_REGISTER_7)),
222+
mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_INT_REQUEST_REGISTER_7)));
223223
}
224224

225225
int vcpu_inject_extint(struct vcpu *vcpu)

‎hypervisor/arch/x86/intr_lapic.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -204,7 +204,7 @@ static void map_lapic(void)
204204
/* At some point we may need to translate this paddr to a vaddr. 1:1
205205
* mapping for now.
206206
*/
207-
lapic_info.xapic.vaddr = (void *)lapic_info.xapic.paddr;
207+
lapic_info.xapic.vaddr = HPA2HVA(lapic_info.xapic.paddr);
208208
}
209209

210210
int early_init_lapic(void)

‎hypervisor/arch/x86/ioapic.c

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ struct ioapic_rte {
4747
struct gsi_table {
4848
uint8_t ioapic_id;
4949
uint8_t pin;
50-
uint64_t addr;
50+
void *addr;
5151
};
5252
static struct gsi_table gsi_table[NR_MAX_GSI];
5353
static int nr_gsi;
@@ -76,17 +76,17 @@ uint16_t legacy_irq_to_pin[NR_LEGACY_IRQ] = {
7676
15, /* IRQ15*/
7777
};
7878

79-
static uint64_t map_ioapic(
79+
static void *map_ioapic(
8080
uint64_t ioapic_paddr)
8181
{
8282
/* At some point we may need to translate this paddr to a vaddr.
8383
* 1:1 mapping for now.
8484
*/
85-
return ioapic_paddr;
85+
return HPA2HVA(ioapic_paddr);
8686
}
8787

8888
static inline uint32_t
89-
ioapic_read_reg32(const uint64_t ioapic_base, const uint8_t offset)
89+
ioapic_read_reg32(const void *ioapic_base, const uint8_t offset)
9090
{
9191
uint32_t v;
9292

@@ -104,7 +104,7 @@ ioapic_read_reg32(const uint64_t ioapic_base, const uint8_t offset)
104104
}
105105

106106
static inline void
107-
ioapic_write_reg32(const uint64_t ioapic_base,
107+
ioapic_write_reg32(const void *ioapic_base,
108108
const uint8_t offset, const uint32_t value)
109109
{
110110
spinlock_rflags;
@@ -138,15 +138,15 @@ get_ioapic_base(int apic_id)
138138

139139

140140
static inline void
141-
ioapic_get_rte_entry(uint64_t ioapic_addr,
141+
ioapic_get_rte_entry(void *ioapic_addr,
142142
int pin, struct ioapic_rte *rte)
143143
{
144144
rte->lo_32 = ioapic_read_reg32(ioapic_addr, pin*2 + 0x10);
145145
rte->hi_32 = ioapic_read_reg32(ioapic_addr, pin*2 + 0x11);
146146
}
147147

148148
static inline void
149-
ioapic_set_rte_entry(uint64_t ioapic_addr,
149+
ioapic_set_rte_entry(void *ioapic_addr,
150150
int pin, struct ioapic_rte *rte)
151151
{
152152
ioapic_write_reg32(ioapic_addr, pin*2 + 0x10, rte->lo_32);
@@ -204,7 +204,7 @@ create_rte_for_gsi_irq(int irq, int vr)
204204

205205
static void ioapic_set_routing(int gsi, int vr)
206206
{
207-
uint64_t addr;
207+
void *addr;
208208
struct ioapic_rte rte;
209209

210210
addr = gsi_table[gsi].addr;
@@ -223,7 +223,7 @@ static void ioapic_set_routing(int gsi, int vr)
223223

224224
void ioapic_get_rte(int irq, uint64_t *rte)
225225
{
226-
uint64_t addr;
226+
void *addr;
227227
struct ioapic_rte _rte;
228228

229229
if (!irq_is_gsi(irq))
@@ -238,7 +238,7 @@ void ioapic_get_rte(int irq, uint64_t *rte)
238238

239239
void ioapic_set_rte(int irq, uint64_t raw_rte)
240240
{
241-
uint64_t addr;
241+
void *addr;
242242
struct ioapic_rte rte;
243243

244244
if (!irq_is_gsi(irq))
@@ -289,7 +289,7 @@ int pin_to_irq(int pin)
289289
void
290290
irq_gsi_mask_unmask(int irq, bool mask)
291291
{
292-
uint64_t addr = gsi_table[irq].addr;
292+
void *addr = gsi_table[irq].addr;
293293
int pin = gsi_table[irq].pin;
294294
struct ioapic_rte rte;
295295

@@ -318,7 +318,7 @@ void setup_ioapic_irq(void)
318318
int pin;
319319
int max_pins;
320320
int version;
321-
uint64_t addr;
321+
void *addr;
322322

323323
addr = map_ioapic(get_ioapic_base(ioapic_id));
324324
version = ioapic_read_reg32(addr, IOAPIC_VER);
@@ -372,7 +372,7 @@ void dump_ioapic(void)
372372
int irq;
373373

374374
for (irq = 0; irq < nr_gsi; irq++) {
375-
uint64_t addr = gsi_table[irq].addr;
375+
void *addr = gsi_table[irq].addr;
376376
int pin = gsi_table[irq].pin;
377377
struct ioapic_rte rte;
378378

@@ -404,7 +404,7 @@ int get_ioapic_info(char *str, int str_max_len)
404404
str += len;
405405

406406
for (irq = 0; irq < nr_gsi; irq++) {
407-
uint64_t addr = gsi_table[irq].addr;
407+
void *addr = gsi_table[irq].addr;
408408
int pin = gsi_table[irq].pin;
409409
struct ioapic_rte rte;
410410

‎hypervisor/arch/x86/mmu.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -468,15 +468,15 @@ static void *walk_paging_struct(void *addr, void *table_base,
468468
return sub_table_addr;
469469
}
470470

471-
void *get_paging_pml4(void)
471+
uint64_t get_paging_pml4(void)
472472
{
473473
/* Return address to caller */
474-
return mmu_pml4_addr;
474+
return HVA2HPA(mmu_pml4_addr);
475475
}
476476

477-
void enable_paging(void *pml4_base_addr)
477+
void enable_paging(uint64_t pml4_base_addr)
478478
{
479-
CPU_CR_WRITE(cr3, (unsigned long)pml4_base_addr);
479+
CPU_CR_WRITE(cr3, pml4_base_addr);
480480
}
481481

482482
void init_paging(void)
@@ -527,7 +527,7 @@ void init_paging(void)
527527
pr_dbg("Enabling MMU ");
528528

529529
/* Enable paging */
530-
enable_paging(mmu_pml4_addr);
530+
enable_paging(HVA2HPA(mmu_pml4_addr));
531531
}
532532

533533
void *alloc_paging_struct(void)

‎hypervisor/arch/x86/vtd.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -219,25 +219,25 @@ static int register_hrhd_units(void)
219219

220220
static uint32_t iommu_read32(struct dmar_drhd_rt *dmar_uint, uint32_t offset)
221221
{
222-
return mmio_read_long((void*)(dmar_uint->drhd->reg_base_addr + offset));
222+
return mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
223223
}
224224

225225
static uint64_t iommu_read64(struct dmar_drhd_rt *dmar_uint, uint32_t offset)
226226
{
227227
uint64_t value;
228228

229-
value = (mmio_read_long((void*)(dmar_uint->drhd->reg_base_addr + offset + 4)));
229+
value = mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4));
230230
value = value << 32;
231-
value = value | (mmio_read_long((void*)(dmar_uint->drhd->reg_base_addr +
232-
offset)));
231+
value = value | mmio_read_long(HPA2HVA(dmar_uint->drhd->reg_base_addr +
232+
offset));
233233

234234
return value;
235235
}
236236

237237
static void iommu_write32(struct dmar_drhd_rt *dmar_uint, uint32_t offset,
238238
uint32_t value)
239239
{
240-
mmio_write_long(value, (void*)(dmar_uint->drhd->reg_base_addr + offset));
240+
mmio_write_long(value, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
241241
}
242242

243243
static void iommu_write64(struct dmar_drhd_rt *dmar_uint, uint32_t offset,
@@ -246,10 +246,10 @@ static void iommu_write64(struct dmar_drhd_rt *dmar_uint, uint32_t offset,
246246
uint32_t temp;
247247

248248
temp = value;
249-
mmio_write_long(temp, (void*)(dmar_uint->drhd->reg_base_addr + offset));
249+
mmio_write_long(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset));
250250

251251
temp = value >> 32;
252-
mmio_write_long(temp, (void*)(dmar_uint->drhd->reg_base_addr + offset + 4));
252+
mmio_write_long(temp, HPA2HVA(dmar_uint->drhd->reg_base_addr + offset + 4));
253253
}
254254

255255
/* flush cache when root table, context table updated */

‎hypervisor/debug/uart16550.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ static inline uint32_t uart16550_read_reg(uint64_t base, uint32_t reg_idx)
9393
if (serial_port_mapped) {
9494
return io_read_byte((uint16_t)base + reg_idx);
9595
} else {
96-
return mmio_read_long((void*)((uint32_t*)base + reg_idx));
96+
return mmio_read_long((void*)((uint32_t*)HPA2HVA(base) + reg_idx));
9797
}
9898
}
9999

@@ -103,7 +103,7 @@ static inline void uart16550_write_reg(uint64_t base,
103103
if (serial_port_mapped) {
104104
io_write_byte(val, (uint16_t)base + reg_idx);
105105
} else {
106-
mmio_write_long(val, (void*)((uint32_t*)base + reg_idx));
106+
mmio_write_long(val, (void*)((uint32_t*)HPA2HVA(base) + reg_idx));
107107
}
108108
}
109109

@@ -339,5 +339,5 @@ void uart16550_set_property(int enabled, int port_mapped, uint64_t base_addr)
339339
{
340340
uart_enabled = enabled;
341341
serial_port_mapped = port_mapped;
342-
Tgt_Uarts[0].base_address = (uint32_t) base_addr;
342+
Tgt_Uarts[0].base_address = base_addr;
343343
}

‎hypervisor/include/arch/x86/mmu.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -314,10 +314,10 @@ struct mem_io_node {
314314
uint64_t range_end;
315315
};
316316

317-
void *get_paging_pml4(void);
317+
uint64_t get_paging_pml4(void);
318318
void *alloc_paging_struct(void);
319319
void free_paging_struct(void *ptr);
320-
void enable_paging(void *pml4_base_addr);
320+
void enable_paging(uint64_t pml4_base_addr);
321321
void init_paging(void);
322322
int map_mem(struct map_params *map_params, void *paddr, void *vaddr,
323323
uint64_t size, uint32_t flags);

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