HV: refine APIC base address to platform acpi info

The base address of LAPIC and IOAPIC should be parsed from MADT table,
so move the definition to platform_acpi_info.h.

Tracked-On: #1500
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

Author: jsun26intel

hypervisor/arch/x86/ioapic.c

@@ -122,24 +122,17 @@ ioapic_write_reg32(const void *ioapic_base,
 	spinlock_irqrestore_release(&ioapic_lock, rflags);
 }
 
+/**
+ * @pre apic_id < 2
+ */
 static inline uint64_t
 get_ioapic_base(uint8_t apic_id)
 {
-	uint64_t addr = 0xffffffffffffffffUL;
-
-	/* should extract next ioapic from ACPI MADT table */
-	if (apic_id == 0U) {
-		addr = DEFAULT_IO_APIC_BASE;
-	} else if (apic_id == 1U) {
-		addr = 0xfec3f000UL;
-	} else if (apic_id == 2U) {
-		addr = 0xfec7f000UL;
-	} else {
-		ASSERT(apic_id <= 2U, "ACPI MADT table missing");
-	}
-	return addr;
-}
+	const uint64_t addr[2] = {IOAPIC0_BASE, IOAPIC1_BASE};
 
+	/* the ioapic base should be extracted from ACPI MADT table */
+	return addr[apic_id];
+}
 
 static inline void
 ioapic_get_rte_entry(void *ioapic_addr,

hypervisor/bsp/include/sbl/platform_acpi_info.h

@@ -13,7 +13,11 @@
 #define ACPI_INFO_VALIDATED
 
 /* APIC */
+#define LAPIC_BASE		0xFEE00000UL
+
 #define NR_IOAPICS		1U
+#define IOAPIC0_BASE		0xFEC00000UL
+#define IOAPIC1_BASE		0UL
 
 /* pm sstate data */
 #define PM1A_EVT_SPACE_ID	SPACE_SYSTEM_IO

hypervisor/bsp/include/uefi/platform_acpi_info.h

@@ -11,7 +11,11 @@
 #define PLATFORM_ACPI_INFO_H
 
 /* APIC */
+#define LAPIC_BASE		0xFEE00000UL
+
 #define NR_IOAPICS		1U
+#define IOAPIC0_BASE		0xFEC00000UL
+#define IOAPIC1_BASE		0UL
 
 /* pm sstate data */
 #define PM1A_EVT_SPACE_ID	SPACE_SYSTEM_IO

hypervisor/include/arch/x86/apicreg.h

@@ -350,9 +350,6 @@ union ioapic_rte {
  * I/O APIC defines
  */
 
-/* default physical locations of an IO APIC */
-#define DEFAULT_IO_APIC_BASE	0xfec00000UL
-
 /* window register offset */
 #define IOAPIC_REGSEL		0x00U
 #define IOAPIC_WINDOW		0x10U

hypervisor/include/arch/x86/lapic.h

@@ -33,9 +33,6 @@
 #define INTR_LAPIC_ICR_ALL_INC_SELF         0x2U
 #define INTR_LAPIC_ICR_ALL_EX_SELF            0x3U
 
-/* Default LAPIC base */
-#define LAPIC_BASE                              0xFEE00000U
-
 /* LAPIC register bit and bitmask definitions */
 #define LAPIC_SVR_VECTOR                        0x000000FFU
 #define LAPIC_SVR_APIC_ENABLE_MASK                   0x00000100U