Skip to content

Commit d67eefb

Browse files
lifeixlijinxia
authored andcommitted
hv: mmu: use get/set_pgentry to get/set page table entry
And remove mem_read/write_xx API. Tracked-On: #1124 Signed-off-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
1 parent 7f9befb commit d67eefb

File tree

2 files changed

+7
-53
lines changed

2 files changed

+7
-53
lines changed

hypervisor/arch/x86/trusty.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -106,21 +106,21 @@ static void create_secure_world_ept(struct vm *vm, uint64_t gpa_orig,
106106
*/
107107
sub_table_addr = alloc_paging_struct();
108108
sworld_pml4e = HVA2HPA(sub_table_addr) | table_present;
109-
mem_write64(pml4_base, sworld_pml4e);
109+
set_pgentry((uint64_t *)pml4_base, sworld_pml4e);
110110

111-
nworld_pml4e = mem_read64(vm->arch_vm.nworld_eptp);
111+
nworld_pml4e = get_pgentry((uint64_t *)vm->arch_vm.nworld_eptp);
112112

113113
/*
114114
* copy PTPDEs from normal world EPT to secure world EPT,
115115
* and remove execute access attribute in these entries
116116
*/
117-
dest_pdpte_p = HPA2HVA(sworld_pml4e & IA32E_REF_MASK);
118-
src_pdpte_p = HPA2HVA(nworld_pml4e & IA32E_REF_MASK);
119-
for (i = 0U; i < IA32E_NUM_ENTRIES - 1; i++) {
120-
pdpte = mem_read64(src_pdpte_p);
117+
dest_pdpte_p = pml4e_page_vaddr(sworld_pml4e);
118+
src_pdpte_p = pml4e_page_vaddr(nworld_pml4e);
119+
for (i = 0U; i < PTRS_PER_PDPTE - 1; i++) {
120+
pdpte = get_pgentry(src_pdpte_p);
121121
if ((pdpte & table_present) != 0UL) {
122122
pdpte &= ~EPT_EXE;
123-
mem_write64(dest_pdpte_p, pdpte);
123+
set_pgentry(dest_pdpte_p, pdpte);
124124
}
125125
src_pdpte_p++;
126126
dest_pdpte_p++;

hypervisor/include/arch/x86/mmu.h

Lines changed: 0 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,6 @@
4040
#define CACHE_LINE_SIZE 64U
4141

4242
/* IA32E Paging constants */
43-
#define IA32E_NUM_ENTRIES 512U
4443
#define IA32E_REF_MASK \
4544
(boot_cpu_data.physical_address_mask)
4645

@@ -66,51 +65,6 @@ enum _page_table_level {
6665
#define PAGE_SIZE_2M MEM_2M
6766
#define PAGE_SIZE_1G MEM_1G
6867

69-
/* Inline functions for reading/writing memory */
70-
static inline uint8_t mem_read8(const void *addr)
71-
{
72-
return *(volatile uint8_t *)(addr);
73-
}
74-
75-
static inline uint16_t mem_read16(const void *addr)
76-
{
77-
return *(volatile uint16_t *)(addr);
78-
}
79-
80-
static inline uint32_t mem_read32(const void *addr)
81-
{
82-
return *(volatile uint32_t *)(addr);
83-
}
84-
85-
static inline uint64_t mem_read64(const void *addr)
86-
{
87-
return *(volatile uint64_t *)(addr);
88-
}
89-
90-
static inline void mem_write8(const void *addr, uint8_t data)
91-
{
92-
volatile uint8_t *addr8 = (volatile uint8_t *)addr;
93-
*addr8 = data;
94-
}
95-
96-
static inline void mem_write16(void *addr, uint16_t data)
97-
{
98-
volatile uint16_t *addr16 = (volatile uint16_t *)addr;
99-
*addr16 = data;
100-
}
101-
102-
static inline void mem_write32(void *addr, uint32_t data)
103-
{
104-
volatile uint32_t *addr32 = (volatile uint32_t *)addr;
105-
*addr32 = data;
106-
}
107-
108-
static inline void mem_write64(void *addr, uint64_t data)
109-
{
110-
volatile uint64_t *addr64 = (volatile uint64_t *)addr;
111-
*addr64 = data;
112-
}
113-
11468
uint64_t get_paging_pml4(void);
11569
void *alloc_paging_struct(void);
11670
void free_paging_struct(void *ptr);

0 commit comments

Comments
 (0)