hv: xsave: remove is_xsave_supported

Update X86_FEATURE_OSXSAVE when enabled and replace is_xsave_supported
with cpu_has_cap(X86_FEATURE_OSXSAVE).

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

Author: lifeix

hypervisor/arch/x86/cpu.c

@@ -761,18 +761,6 @@ bool is_vapic_virt_reg_supported(void)
 	return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_REG) != 0);
 }
 
-bool is_xsave_supported(void)
-{
-	/*
-	 *todo:
-	 *below flag also should be tested, but current it will be false
-	 *as it is not updated after turning on the host's CR4.OSXSAVE bit,
-	 *will be fixed in cpuid related patch.
-	 *boot_cpu_data.cpuid_leaves[FEAT_1_ECX] & CPUID_ECX_OSXSAVE
-	 **/
-	return !!(boot_cpu_data.cpuid_leaves[FEAT_1_ECX] & CPUID_ECX_XSAVE);
-}
-
 static void cpu_xsave_init(void)
 {
 	uint64_t val64;
@@ -781,5 +769,15 @@ static void cpu_xsave_init(void)
 		CPU_CR_READ(cr4, &val64);
 		val64 |= CR4_OSXSAVE;
 		CPU_CR_WRITE(cr4, val64);
+
+		if (get_cpu_id() == CPU_BOOT_ID) {
+			uint32_t ecx, unused;
+			cpuid(CPUID_FEATURES, &unused, &unused, &ecx, &unused);
+
+			/* if set, update it */
+			if (ecx & CPUID_ECX_OSXSAVE)
+				boot_cpu_data.cpuid_leaves[FEAT_1_ECX] |=
+						CPUID_ECX_OSXSAVE;
+		}
 	}
 }

hypervisor/arch/x86/cpuid.c

@@ -356,7 +356,7 @@ void guest_cpuid(struct vcpu *vcpu,
 		break;
 
 	case 0x0d:
-		if (!is_xsave_supported()) {
+		if (!cpu_has_cap(X86_FEATURE_OSXSAVE)) {
 			*eax = 0;
 			*ebx = 0;
 			*ecx = 0;

hypervisor/arch/x86/vmx.c

@@ -933,7 +933,7 @@ static void init_exec_ctrl(struct vcpu *vcpu)
 			exec_vmwrite(VMX_TPR_THRESHOLD, 0);
 	}
 
-	if (is_xsave_supported()) {
+	if (cpu_has_cap(X86_FEATURE_OSXSAVE)) {
 		exec_vmwrite64(VMX_XSS_EXITING_BITMAP_FULL, 0);
 		value32 |= VMX_PROCBASED_CTLS2_XSVE_XRSTR;
 	}

hypervisor/include/arch/x86/cpu.h

@@ -258,7 +258,6 @@ int hv_main(int cpu_id);
 bool is_vapic_supported(void);
 bool is_vapic_intr_delivery_supported(void);
 bool is_vapic_virt_reg_supported(void);
-bool is_xsave_supported(void);
 bool cpu_has_cap(uint32_t bit);
 
 /* Read control register */