hv: self-IPI APIC register in x2APIC mode of guest vLAPIC

This patch adds support for self-IPI virtualization when guest
uses vLAPIC in x2APIC mode.

Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>

Author: Sainath Grandhi

hypervisor/arch/x86/guest/vlapic.c

@@ -2374,6 +2374,18 @@ int veoi_vmexit_handler(struct vcpu *vcpu)
 	return 0;
 }
 
+static void vlapic_x2apic_self_ipi_handler(struct acrn_vlapic *vlapic)
+{
+	struct lapic_regs *lapic;
+	uint32_t vector;
+	struct vcpu *target_vcpu;
+
+	lapic = &(vlapic->apic_page);
+	vector = lapic->self_ipi.v & 0xFFU;
+	target_vcpu = vlapic->vcpu;
+	vlapic_set_intr(target_vcpu, vector, LAPIC_TRIG_EDGE);
+}
+
 int apic_write_vmexit_handler(struct vcpu *vcpu)
 {
 	uint64_t qual;
@@ -2428,6 +2440,11 @@ int apic_write_vmexit_handler(struct vcpu *vcpu)
 	case APIC_OFFSET_TIMER_DCR:
 		vlapic_dcr_write_handler(vlapic);
 		break;
+	case APIC_OFFSET_SELF_IPI:
+		if (is_x2apic_enabled(vlapic)) {
+			vlapic_x2apic_self_ipi_handler(vlapic);
+		}
+		break;
 	default:
 		handled = 0;
 		pr_err("Unhandled APIC-Write, offset:0x%x", offset);

hypervisor/arch/x86/guest/vlapic_priv.h

@@ -80,6 +80,6 @@
 #define APIC_OFFSET_TIMER_ICR	0x380U	/* Timer's Initial Count	*/
 #define APIC_OFFSET_TIMER_CCR	0x390U	/* Timer's Current Count	*/
 #define APIC_OFFSET_TIMER_DCR	0x3E0U	/* Timer's Divide Configuration	*/
-
+#define APIC_OFFSET_SELF_IPI    0x3F0U  /* Self IPI Register */
 
 #endif /* VLAPIC_PRIV_H */

hypervisor/include/arch/x86/apicreg.h

@@ -72,7 +72,7 @@ struct lapic_regs {			 /*OFFSET(Hex)*/
 	struct lapic_reg	ccr_timer;/*390*/
 	struct lapic_reg	rsv3[4];
 	struct lapic_reg	dcr_timer;/*3E0*/
-	struct lapic_reg	rsv4;
+	struct lapic_reg	self_ipi; /*3F0*/
 
 	/*roundup sizeof current struct to 4KB*/
 	struct lapic_reg	rsv5[192]; /*400 -- FF0*/