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hv: ptdev: simplify ptdev_intx_pin_remap logic
Since this interrupt pin is passed through to the guest, we could set it as we like. There's no need a flag to emulate the masked status. Signed-off-by: Li, Fei1 <fei1.li@intel.com>
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-42
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+10
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hypervisor/arch/x86/assign.c

Lines changed: 10 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -663,26 +663,29 @@ static void activate_physical_ioapic(struct vm *vm,
663663
{
664664
union ioapic_rte rte;
665665
uint32_t phys_irq = entry->allocated_pirq;
666+
uint32_t intr_mask;
666667
bool is_lvl_trigger = false;
667668

668669
/* disable interrupt */
669670
GSI_MASK_IRQ(phys_irq);
670671

671672
/* build physical IOAPIC RTE */
672673
rte = ptdev_build_physical_rte(vm, entry);
673-
674-
/* set rte entry */
675-
rte.full |= IOAPIC_RTE_INTMSET;
676-
ioapic_set_rte(phys_irq, rte);
674+
intr_mask = (rte.full & IOAPIC_RTE_INTMASK);
677675

678676
/* update irq trigger mode according to info in guest */
679677
if ((rte.full & IOAPIC_RTE_TRGRMOD) == IOAPIC_RTE_TRGRLVL) {
680678
is_lvl_trigger = true;
681679
}
682680
set_irq_trigger_mode(phys_irq, is_lvl_trigger);
683681

684-
/* enable interrupt */
685-
GSI_UNMASK_IRQ(phys_irq);
682+
/* set rte entry when masked */
683+
rte.full |= IOAPIC_RTE_INTMSET;
684+
ioapic_set_rte(phys_irq, rte);
685+
686+
if (intr_mask == IOAPIC_RTE_INTMCLR) {
687+
GSI_UNMASK_IRQ(phys_irq);
688+
}
686689
}
687690

688691
/* Main entry for PCI/Legacy device assignment with INTx, calling from vIOAPIC
@@ -691,7 +694,6 @@ static void activate_physical_ioapic(struct vm *vm,
691694
int ptdev_intx_pin_remap(struct vm *vm, struct ptdev_intx_info *info)
692695
{
693696
struct ptdev_remapping_info *entry;
694-
union ioapic_rte rte;
695697
uint32_t phys_irq;
696698
uint8_t phys_pin;
697699
bool need_switch_vpin_src = false;
@@ -800,41 +802,7 @@ int ptdev_intx_pin_remap(struct vm *vm, struct ptdev_intx_info *info)
800802
intx->vpin_src = info->vpin_src;
801803
intx->virt_pin = info->virt_pin;
802804
}
803-
804-
if (is_entry_active(entry)
805-
&& (intx->vpin_src
806-
== PTDEV_VPIN_IOAPIC)) {
807-
vioapic_get_rte(vm, intx->virt_pin, &rte);
808-
if (rte.u.lo_32 == 0x10000U) {
809-
/* disable interrupt */
810-
GSI_MASK_IRQ(phys_irq);
811-
dev_dbg(ACRN_DBG_IRQ,
812-
"IOAPIC pin=%hhu pirq=%u deassigned ",
813-
phys_pin, phys_irq);
814-
dev_dbg(ACRN_DBG_IRQ, "from vm%d vIOAPIC vpin=%d",
815-
entry->vm->vm_id,
816-
intx->virt_pin);
817-
goto END;
818-
} else {
819-
/*update rte*/
820-
activate_physical_ioapic(vm, entry);
821-
}
822-
} else if (is_entry_active(entry)
823-
&& (intx->vpin_src == PTDEV_VPIN_PIC)) {
824-
/* only update here
825-
* deactive vPIC entry when IOAPIC take it over
826-
*/
827-
activate_physical_ioapic(vm, entry);
828-
} else {
829-
activate_physical_ioapic(vm, entry);
830-
831-
dev_dbg(ACRN_DBG_IRQ,
832-
"IOAPIC pin=%hhu pirq=%u assigned to vm%d %s vpin=%d",
833-
phys_pin, phys_irq, entry->vm->vm_id,
834-
intx->vpin_src == PTDEV_VPIN_PIC ?
835-
"vPIC" : "vIOAPIC",
836-
intx->virt_pin);
837-
}
805+
activate_physical_ioapic(vm, entry);
838806
END:
839807
return 0;
840808
}

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