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lifeixwenlingz
lifeix
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hv: vlapic: remove vlapic_rdmsr/wrmsr
We could call vlapic API directly, remove vlapic_rdmsr/wrmsr to make things easier. Tracked-On: #1842 Signed-off-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
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3 files changed

+49
-95
lines changed

3 files changed

+49
-95
lines changed

‎hypervisor/arch/x86/guest/vlapic.c

Lines changed: 37 additions & 87 deletions
Original file line numberDiff line numberDiff line change
@@ -401,7 +401,7 @@ static void vlapic_icrtmr_write_handler(struct acrn_vlapic *vlapic)
401401
}
402402
}
403403

404-
static uint64_t vlapic_get_tsc_deadline_msr(const struct acrn_vlapic *vlapic)
404+
uint64_t vlapic_get_tsc_deadline_msr(const struct acrn_vlapic *vlapic)
405405
{
406406
uint64_t ret;
407407
if (!vlapic_lvtt_tsc_deadline(vlapic)) {
@@ -415,8 +415,7 @@ static uint64_t vlapic_get_tsc_deadline_msr(const struct acrn_vlapic *vlapic)
415415

416416
}
417417

418-
static void vlapic_set_tsc_deadline_msr(struct acrn_vlapic *vlapic,
419-
uint64_t val_arg)
418+
void vlapic_set_tsc_deadline_msr(struct acrn_vlapic *vlapic, uint64_t val_arg)
420419
{
421420
struct hv_timer *timer;
422421
uint64_t val = val_arg;
@@ -1754,17 +1753,13 @@ void vlapic_restore(struct acrn_vlapic *vlapic, const struct lapic_regs *regs)
17541753
vlapic_dcr_write_handler(vlapic);
17551754
}
17561755

1757-
static uint64_t
1758-
vlapic_get_apicbase(const struct acrn_vlapic *vlapic)
1756+
uint64_t vlapic_get_apicbase(const struct acrn_vlapic *vlapic)
17591757
{
1760-
17611758
return vlapic->msr_apicbase;
17621759
}
17631760

1764-
static int32_t
1765-
vlapic_set_apicbase(struct acrn_vlapic *vlapic, uint64_t new)
1761+
int32_t vlapic_set_apicbase(struct acrn_vlapic *vlapic, uint64_t new)
17661762
{
1767-
17681763
int32_t ret = 0;
17691764
uint64_t changed;
17701765
changed = vlapic->msr_apicbase ^ new;
@@ -2046,8 +2041,7 @@ vlapic_x2apic_pt_icr_access(struct acrn_vm *vm, uint64_t val)
20462041
return ret;
20472042
}
20482043

2049-
static int32_t vlapic_x2apic_access(struct acrn_vcpu *vcpu, uint32_t msr, bool write,
2050-
uint64_t *val)
2044+
int32_t vlapic_x2apic_read(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t *val)
20512045
{
20522046
struct acrn_vlapic *vlapic;
20532047
uint32_t offset;
@@ -2061,99 +2055,55 @@ static int32_t vlapic_x2apic_access(struct acrn_vcpu *vcpu, uint32_t msr, bool w
20612055
if (is_x2apic_enabled(vlapic)) {
20622056
if (is_lapic_pt(vcpu->vm)) {
20632057
switch (msr) {
2064-
case MSR_IA32_EXT_APIC_ICR:
2065-
error = vlapic_x2apic_pt_icr_access(vcpu->vm, *val);
2066-
break;
2067-
case MSR_IA32_EXT_APIC_LDR:
2068-
case MSR_IA32_EXT_XAPICID:
2069-
if (!write) {
2070-
offset = x2apic_msr_to_regoff(msr);
2071-
error = vlapic_read(vlapic, offset, val);
2072-
}
2073-
break;
2074-
default:
2075-
pr_err("%s: unexpected MSR[0x%x] access with lapic_pt", __func__, msr);
2076-
break;
2058+
case MSR_IA32_EXT_APIC_LDR:
2059+
case MSR_IA32_EXT_XAPICID:
2060+
offset = x2apic_msr_to_regoff(msr);
2061+
error = vlapic_read(vlapic, offset, val);
2062+
break;
2063+
default:
2064+
pr_err("%s: unexpected MSR[0x%x] read with lapic_pt", __func__, msr);
2065+
break;
20772066
}
20782067
} else {
2079-
offset = x2apic_msr_to_regoff(msr);
2080-
if (write) {
2081-
if (!is_x2apic_read_only_msr(msr)) {
2082-
error = vlapic_write(vlapic, offset, *val);
2083-
}
2084-
} else {
2085-
if (!is_x2apic_write_only_msr(msr)) {
2086-
error = vlapic_read(vlapic, offset, val);
2087-
}
2068+
if (!is_x2apic_write_only_msr(msr)) {
2069+
offset = x2apic_msr_to_regoff(msr);
2070+
error = vlapic_read(vlapic, offset, val);
20882071
}
20892072
}
20902073
}
20912074

20922075
return error;
20932076
}
20942077

2095-
int32_t
2096-
vlapic_rdmsr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t *rval)
2097-
{
2098-
int32_t error = 0;
2099-
struct acrn_vlapic *vlapic;
2100-
2101-
dev_dbg(ACRN_DBG_LAPIC, "cpu[%hu] rdmsr: %x", vcpu->vcpu_id, msr);
2102-
vlapic = vcpu_vlapic(vcpu);
2103-
2104-
switch (msr) {
2105-
case MSR_IA32_APIC_BASE:
2106-
*rval = vlapic_get_apicbase(vlapic);
2107-
break;
2108-
2109-
case MSR_IA32_TSC_DEADLINE:
2110-
*rval = vlapic_get_tsc_deadline_msr(vlapic);
2111-
break;
2112-
2113-
default:
2114-
if (is_x2apic_msr(msr)) {
2115-
error = vlapic_x2apic_access(vcpu, msr, false, rval);
2116-
} else {
2117-
error = -1;
2118-
dev_dbg(ACRN_DBG_LAPIC,
2119-
"Invalid vlapic msr 0x%x access\n", msr);
2120-
}
2121-
break;
2122-
}
2123-
2124-
return error;
2125-
}
2126-
2127-
int32_t
2128-
vlapic_wrmsr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t wval)
2078+
int32_t vlapic_x2apic_write(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t val)
21292079
{
2130-
int32_t error = 0;
21312080
struct acrn_vlapic *vlapic;
2081+
uint32_t offset;
2082+
int32_t error = -1;
21322083

2084+
/*
2085+
* If vLAPIC is in xAPIC mode and guest tries to access x2APIC MSRs
2086+
* inject a GP to guest
2087+
*/
21332088
vlapic = vcpu_vlapic(vcpu);
2134-
2135-
switch (msr) {
2136-
case MSR_IA32_APIC_BASE:
2137-
error = vlapic_set_apicbase(vlapic, wval);
2138-
break;
2139-
2140-
case MSR_IA32_TSC_DEADLINE:
2141-
vlapic_set_tsc_deadline_msr(vlapic, wval);
2142-
break;
2143-
2144-
default:
2145-
if (is_x2apic_msr(msr)) {
2146-
error = vlapic_x2apic_access(vcpu, msr, true, &wval);
2089+
if (is_x2apic_enabled(vlapic)) {
2090+
if (is_lapic_pt(vcpu->vm)) {
2091+
switch (msr) {
2092+
case MSR_IA32_EXT_APIC_ICR:
2093+
error = vlapic_x2apic_pt_icr_access(vcpu->vm, val);
2094+
break;
2095+
default:
2096+
pr_err("%s: unexpected MSR[0x%x] write with lapic_pt", __func__, msr);
2097+
break;
2098+
}
21472099
} else {
2148-
error = -1;
2149-
dev_dbg(ACRN_DBG_LAPIC,
2150-
"Invalid vlapic msr 0x%x access\n", msr);
2100+
if (!is_x2apic_read_only_msr(msr)) {
2101+
offset = x2apic_msr_to_regoff(msr);
2102+
error = vlapic_write(vlapic, offset, val);
2103+
}
21512104
}
2152-
break;
21532105
}
21542106

2155-
dev_dbg(ACRN_DBG_LAPIC, "cpu[%hu] wrmsr: %x wval=%#x",
2156-
vcpu->vcpu_id, msr, wval);
21572107
return error;
21582108
}
21592109

‎hypervisor/arch/x86/guest/vmsr.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -388,7 +388,7 @@ int32_t rdmsr_vmexit_handler(struct acrn_vcpu *vcpu)
388388
switch (msr) {
389389
case MSR_IA32_TSC_DEADLINE:
390390
{
391-
err = vlapic_rdmsr(vcpu, msr, &v);
391+
v = vlapic_get_tsc_deadline_msr(vcpu_vlapic(vcpu));
392392
break;
393393
}
394394
case MSR_IA32_TSC_ADJUST:
@@ -435,7 +435,7 @@ int32_t rdmsr_vmexit_handler(struct acrn_vcpu *vcpu)
435435
case MSR_IA32_APIC_BASE:
436436
{
437437
/* Read APIC base */
438-
err = vlapic_rdmsr(vcpu, msr, &v);
438+
v = vlapic_get_apicbase(vcpu_vlapic(vcpu));
439439
break;
440440
}
441441
case MSR_IA32_FEATURE_CONTROL:
@@ -446,7 +446,7 @@ int32_t rdmsr_vmexit_handler(struct acrn_vcpu *vcpu)
446446
default:
447447
{
448448
if (is_x2apic_msr(msr)) {
449-
err = vlapic_rdmsr(vcpu, msr, &v);
449+
err = vlapic_x2apic_read(vcpu, msr, &v);
450450
} else {
451451
pr_warn("%s(): vm%d vcpu%d reading MSR %lx not supported",
452452
__func__, vcpu->vm->vm_id, vcpu->vcpu_id, msr);
@@ -526,7 +526,7 @@ int32_t wrmsr_vmexit_handler(struct acrn_vcpu *vcpu)
526526
switch (msr) {
527527
case MSR_IA32_TSC_DEADLINE:
528528
{
529-
err = vlapic_wrmsr(vcpu, msr, v);
529+
vlapic_set_tsc_deadline_msr(vcpu_vlapic(vcpu), v);
530530
break;
531531
}
532532
case MSR_IA32_TSC_ADJUST:
@@ -586,7 +586,7 @@ int32_t wrmsr_vmexit_handler(struct acrn_vcpu *vcpu)
586586
}
587587
case MSR_IA32_APIC_BASE:
588588
{
589-
err = vlapic_wrmsr(vcpu, msr, v);
589+
err = vlapic_set_apicbase(vcpu_vlapic(vcpu), v);
590590
break;
591591
}
592592
case MSR_IA32_FEATURE_CONTROL:
@@ -597,7 +597,7 @@ int32_t wrmsr_vmexit_handler(struct acrn_vcpu *vcpu)
597597
default:
598598
{
599599
if (is_x2apic_msr(msr)) {
600-
err = vlapic_wrmsr(vcpu, msr, v);
600+
err = vlapic_x2apic_write(vcpu, msr, v);
601601
} else {
602602
pr_warn("%s(): vm%d vcpu%d writing MSR %lx not supported",
603603
__func__, vcpu->vm->vm_id, vcpu->vcpu_id, msr);

‎hypervisor/include/arch/x86/guest/vlapic.h

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -165,8 +165,12 @@ void vlapic_get_deliverable_intr(struct acrn_vlapic *vlapic, uint32_t vector);
165165
*/
166166
uint64_t apicv_get_pir_desc_paddr(struct acrn_vcpu *vcpu);
167167

168-
int32_t vlapic_rdmsr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t *rval);
169-
int32_t vlapic_wrmsr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t wval);
168+
uint64_t vlapic_get_tsc_deadline_msr(const struct acrn_vlapic *vlapic);
169+
void vlapic_set_tsc_deadline_msr(struct acrn_vlapic *vlapic, uint64_t val_arg);
170+
uint64_t vlapic_get_apicbase(const struct acrn_vlapic *vlapic);
171+
int32_t vlapic_set_apicbase(struct acrn_vlapic *vlapic, uint64_t new);
172+
int32_t vlapic_x2apic_read(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t *val);
173+
int32_t vlapic_x2apic_write(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t val);
170174

171175
/*
172176
* Signals to the LAPIC that an interrupt at 'vector' needs to be generated

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