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This repository has been archived by the owner on Jan 16, 2020. It is now read-only.
Having a hint that all is not well with the crossbar, I tried simulating in the verification environment that is provided for Xilinx crossbar. The Xilinx crossbar passes but this one gives the following errors:
(The references to PASSED refer to the Xilinx crossbar that runs in parallel for comparison)
A test case is available but after minimisation it was still too large to upload here.
Chronologic VCS simulator copyright 1991-2017
Contains Synopsys proprietary information.
Compiler version M-2017.03-SP2-5_Full64; Runtime version M-2017.03-SP2-5_Full64; Nov 13 12:07 2018
0: exdes_tb: Starting testbench
0: exdes_tb: System reset detected: 1
2500000: exdes_tb: System reset detected: 0
7885000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 79) : ERROR : AXI_AUXM_RCAM_UNDERFLOW. Read CAM underflow.
$stop at time 7885000 Scope: exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP File: ./../../axi_crossbar_0_ex/axi_crossbar_0_ex.ip_user_files/ipstatic/hdl/axi_protocol_checker_v2_0_vl_rfs.sv Line: 5250
ucli% run
7985000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 58) : ERROR : Invalid state x
7985000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 59) : ERROR : AXI_ERRS_RID: A slave can only give read data with an ID to match an outstanding read transaction. Spec: section A5.3.1.
$stop at time 7985000 Scope: exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP File: ./../../axi_crossbar_0_ex/axi_crossbar_0_ex.ip_user_files/ipstatic/hdl/axi_protocol_checker_v2_0_vl_rfs.sv Line: 5230
ucli%
ucli%
ucli% run
8485000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 32) : ERROR : AXI_ERRS_BRESP_AW: A slave must not give a write response before the write address. Spec: section A3.3.1 and figure A3-7.
$stop at time 8485000 Scope: exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP File: ./../../axi_crossbar_0_ex/axi_crossbar_0_ex.ip_user_files/ipstatic/hdl/axi_protocol_checker_v2_0_vl_rfs.sv Line: 5203
ucli% run
92085000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 58) : ERROR : AXI_ERRS_RDATA_NUM: The number of read data items must match the corresponding ARLEN. Spec: section A3.4.1.
$stop at time 92085000 Scope: exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP File: ./../../axi_crossbar_0_ex/axi_crossbar_0_ex.ip_user_files/ipstatic/hdl/axi_protocol_checker_v2_0_vl_rfs.sv Line: 5229
ucli% run
147090000: exdes_tb: SIMULATION PASSED
147090000: exdes_tb: Test Completed Successfully
$stop at time 147090000 Scope: exdes_tb File: ./../imports/axi_crossbar_0_example_design_tb.v Line: 102
ucli% run
147095000: exdes_tb: SIMULATION PASSED
147095000: exdes_tb: Test Completed Successfully
$stop at time 147095000 Scope: exdes_tb File: ./../imports/axi_crossbar_0_example_design_tb.v Line: 102
ucli% exit
V C S S i m u l a t i o n R e p o r t
Time: 147095000 ps
CPU Time: 1.380 seconds; Data structure size: 3.0Mb
Tue Nov 13 12:07:33 2018
The text was updated successfully, but these errors were encountered:
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Having a hint that all is not well with the crossbar, I tried simulating in the verification environment that is provided for Xilinx crossbar. The Xilinx crossbar passes but this one gives the following errors:
(The references to PASSED refer to the Xilinx crossbar that runs in parallel for comparison)
A test case is available but after minimisation it was still too large to upload here.
Chronologic VCS simulator copyright 1991-2017
Contains Synopsys proprietary information.
Compiler version M-2017.03-SP2-5_Full64; Runtime version M-2017.03-SP2-5_Full64; Nov 13 12:07 2018
0: exdes_tb: Starting testbench
0: exdes_tb: System reset detected: 1
2500000: exdes_tb: System reset detected: 0
7885000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 79) : ERROR : AXI_AUXM_RCAM_UNDERFLOW. Read CAM underflow.
$stop at time 7885000 Scope: exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP File: ./../../axi_crossbar_0_ex/axi_crossbar_0_ex.ip_user_files/ipstatic/hdl/axi_protocol_checker_v2_0_vl_rfs.sv Line: 5250
ucli% run
7985000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 58) : ERROR : Invalid state x
7985000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 59) : ERROR : AXI_ERRS_RID: A slave can only give read data with an ID to match an outstanding read transaction. Spec: section A5.3.1.
$stop at time 7985000 Scope: exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP File: ./../../axi_crossbar_0_ex/axi_crossbar_0_ex.ip_user_files/ipstatic/hdl/axi_protocol_checker_v2_0_vl_rfs.sv Line: 5230
ucli%
ucli%
ucli% run
8485000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 32) : ERROR : AXI_ERRS_BRESP_AW: A slave must not give a write response before the write address. Spec: section A3.3.1 and figure A3-7.
$stop at time 8485000 Scope: exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP File: ./../../axi_crossbar_0_ex/axi_crossbar_0_ex.ip_user_files/ipstatic/hdl/axi_protocol_checker_v2_0_vl_rfs.sv Line: 5203
ucli% run
92085000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 58) : ERROR : AXI_ERRS_RDATA_NUM: The number of read data items must match the corresponding ARLEN. Spec: section A3.4.1.
$stop at time 92085000 Scope: exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP File: ./../../axi_crossbar_0_ex/axi_crossbar_0_ex.ip_user_files/ipstatic/hdl/axi_protocol_checker_v2_0_vl_rfs.sv Line: 5229
ucli% run
147090000: exdes_tb: SIMULATION PASSED
147090000: exdes_tb: Test Completed Successfully
$stop at time 147090000 Scope: exdes_tb File: ./../imports/axi_crossbar_0_example_design_tb.v Line: 102
ucli% run
147095000: exdes_tb: SIMULATION PASSED
147095000: exdes_tb: Test Completed Successfully
$stop at time 147095000 Scope: exdes_tb File: ./../imports/axi_crossbar_0_example_design_tb.v Line: 102
ucli% exit
V C S S i m u l a t i o n R e p o r t
Time: 147095000 ps
CPU Time: 1.380 seconds; Data structure size: 3.0Mb
Tue Nov 13 12:07:33 2018
The text was updated successfully, but these errors were encountered: