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Major core register refactoring #933

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Aug 16, 2020
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@flit flit commented Aug 15, 2020

This PR refactors the core register related code out of CortexM and into a set of classes with an architecture-independent base. The old CORE_REGISTER dict is gone. CortexM and subclasses provide a new core_registers property that is a CoreRegistersIndex object which gives you multiple ways to access core registers. Each core register is represented by a CoreRegisterInfo object.

Detailed changes:

  • Added architecture-independent common classes to hold information about core registers in core/core_registers.py.
  • Moved Cortex-M core register definitions to coresight/cortex_m_core_registers.py.
  • CortexM has a core_registers property that is a CoreRegistersIndex with all registers available for the given core instance.
  • Raising CoreRegisterAccessError on failure to read/write core reg, instead of the annoying assertion failure.
  • Added check for the core being halted before attempting to read/write core regs, since the behaviour is unpredictable when the core is running. If the core is not halted, CoreRegisterAccessError is raised.
  • Fixed assumptions in GDBContextFacade about gdb regnum and offsets in the gdb register context data with deterministic implementation.
  • Moved target XML generated to GDBContextFacade.
  • The register cache handles reads and writes while the core is running slightly better.
  • Added test cases to cortex_test.py.
  • Commander reg command improvements:
    • It accepts the name of a register group or a unique prefix thereof and will print the whole group.
    • Dynamic formatting of registers in columns based on the terminal width (or 80 cols for non-tty output).
    • 'show register-groups' command.
  • Added some v8-M core registers like MSPLIM, PSPLIM, and related variants.
  • Detecting the v8.1-M MVE extension.
  • Added VPR register for MVE.
  • Updated other code to match changes.

There are still some architecture-dependent sections of code that deals with core registers. Specifically, the register cache and RTOSes are dependent on Cortex-M registers.

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flit commented Aug 15, 2020

/morph test

- Added architecture-independent common classes to hold information about
  core registers in core/core_registers.py.
- Moved Cortex-M core register definitions to cortex_m_core_registers.py.
- CortexM has a 'core_registers' property that is a CoreRegistersIndex
  with all registers available for the given core instance.
- Raising CoreRegisterAccessError on failure to read/write core reg.
- Fixed assumptions in GDBContextFacade about gdb regnum and offsets in
  the gdb register context data with deterministic implementation.
- Updated other code to match changes.
- Verify r/w core regs while running raises exception.
- Verify that all core registers can be read and written.
- Aligned printed timings for simulated gdb operations.
- If the core is running during a register write, pass the write directly
  to the context.
- A read while the core is running will invalidate the cache, then the
  read is passed to the context.
- 'show register-groups' command.
- 'reg' accepts a unique prefix of a register group.
- Registers are printed in columns, sorted naturally, and grouped by
  their register group.
- Refactor core register formatting into one method.
- If a register's gdb type is code_ptr or data_ptr, only the hex form
  is printed.
- Added ColumnFormatter, UniquePrefixMatcher, and round_up_div() utilities.
- Added some core registers like MSPLIM and related.
- Added extension enums for v8.1 security additions and MVE FP support.
- Detecting the MVE extension.
- Added VPR register for MVE.
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flit commented Aug 16, 2020

/morph test

@flit flit merged commit 33024ad into pyocd:master Aug 16, 2020
@flit flit deleted the feature/core_reg_plus branch October 29, 2021 19:06
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