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This PR refactors the core register related code out of
CortexM
and into a set of classes with an architecture-independent base. The oldCORE_REGISTER
dict is gone.CortexM
and subclasses provide a newcore_registers
property that is aCoreRegistersIndex
object which gives you multiple ways to access core registers. Each core register is represented by aCoreRegisterInfo
object.Detailed changes:
core/core_registers.py
.coresight/cortex_m_core_registers.py
.CortexM
has acore_registers
property that is aCoreRegistersIndex
with all registers available for the given core instance.CoreRegisterAccessError
on failure to read/write core reg, instead of the annoying assertion failure.CoreRegisterAccessError
is raised.GDBContextFacade
about gdb regnum and offsets in the gdb register context data with deterministic implementation.GDBContextFacade
.cortex_test.py
.reg
command improvements:There are still some architecture-dependent sections of code that deals with core registers. Specifically, the register cache and RTOSes are dependent on Cortex-M registers.