Reduce prefetch SM usage when using pipeline prefetching #2991
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August 14, 2024 16:27
Differential Revision: D61294287
Differential Revision: D60727327
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This pull request was exported from Phabricator. Differential Revision: D61145930 |
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Summary: Pull Request resolved: pytorch#2991 This diff limits the SM usage on `masked_index_put` and `masked_index_get` when pipeline prefetching is used by using a small grid size. This is to reduce the interference of these kernels with the kernels on the compute stream during prefetch. The grid size is currently set to 1/8 of the total number of SMs. However, this number has to be tuned. Differential Revision: D61145930
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Summary: Pull Request resolved: pytorch#2991 This diff limits the SM usage on `masked_index_put` and `masked_index_get` when pipeline prefetching is used by using a small grid size. This is to reduce the interference of these kernels with the kernels on the compute stream during prefetch. The grid size is currently set to 1/8 of the total number of SMs. However, this number has to be tuned. Differential Revision: D61145930
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Summary:
This diff limits the SM usage on
masked_index_putandmasked_index_getwhen pipeline prefetching is used by using a smallgrid size. This is to reduce the interference of these kernels with
the kernels on the compute stream during prefetch. The grid size is
currently set to 1/8 of the total number of SMs. However, this number
has to be tuned.
Differential Revision: D61145930