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Now that the hardware changes have landed in recent Urukul hw_revs, we can consider redesigning the CPLD gateware and the ARTIQ coredevice layer to expose more features and expose the existing ones in a better way.
Now that the hardware changes have landed in recent Urukul hw_revs, we can consider redesigning the CPLD gateware and the ARTIQ coredevice layer to expose more features and expose the existing ones in a better way.
Precursor changes:
Potential tasks
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