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Redesign #7

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5 tasks
jordens opened this issue Jul 24, 2019 · 0 comments
Open
5 tasks

Redesign #7

jordens opened this issue Jul 24, 2019 · 0 comments
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S-for-contract

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@jordens
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jordens commented Jul 24, 2019 •
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Now that the hardware changes have landed in recent Urukul hw_revs, we can consider redesigning the CPLD gateware and the ARTIQ coredevice layer to expose more features and expose the existing ones in a better way.

Precursor changes:

Potential tasks

  • Mirny-style SPI address-CS demux
  • decouple channels
  • implement independent profile/osk/attenuator
  • DRG
  • better RAM usage pattern
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