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WIP: OMAP4: add coresight components
The base address are from Table 2-2 L3_EMU Memory Space Mapping of the OMAP4430 TRM and the connections are from Figure 28-2 Processor Trace Flow of the same document. https://focus.ti.com/pdfs/wtbu/OMAP4430_ES2.0_Public_TRM_vJ.pdf This is also a very useful reference: http://www2.lauterbach.com/pdf/arm_app_coresight.pdf === HWMOD Hacks The hacks to enable all HWMODs are to enable the required clocks. The clocks required are as described here: http://permalink.gmane.org/gmane.linux.ports.arm.kernel/112477 and equivalent to these register writes: The presence of the PERIPHID can be used to check if the correct clocks have been enabled (the drivers won't probe otherwise): 0x00000090 === Usage Read "How to use" in Documentation/trace/coresight.txt. This works: === Decoding These tools decode something: ./ptm2human -i ~/trace.bin -c 4 https://github.com/hwangcc23/ptm2human python etm-objdump.py trace.bin --trace-decoder-options="--pft-1.1" https://lists.linaro.org/pipermail/linaro-dev/2012-November/014439.html
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‎arch/arm/boot/dts/omap4.dtsi‎

Lines changed: 177 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@
3131
#address-cells = <1>;
3232
#size-cells = <0>;
3333

34-
cpu@0 {
34+
CPU0: cpu@0 {
3535
compatible = "arm,cortex-a9";
3636
device_type = "cpu";
3737
next-level-cache = <&L2>;
@@ -42,7 +42,7 @@
4242

4343
clock-latency = <300000>; /* From omap-cpufreq driver */
4444
};
45-
cpu@1 {
45+
CPU1: cpu@1 {
4646
compatible = "arm,cortex-a9";
4747
device_type = "cpu";
4848
next-level-cache = <&L2>;
@@ -124,6 +124,181 @@
124124
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
125125
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
126126

127+
ptm@5414c000 {
128+
compatible = "arm,coresight-etm3x", "arm,primecell";
129+
reg = <0x5414c000 0x1000>;
130+
ti,hwmods = "l3_main_3", "l3_instr", "debugss";
131+
132+
clocks = <&trace_clk_div_ck>;
133+
clock-names = "apb_pclk";
134+
cpu = <&CPU0>;
135+
port {
136+
ptm0_out_port: endpoint {
137+
remote-endpoint = <&mpu_funnel_in_port0>;
138+
};
139+
};
140+
};
141+
142+
ptm@5414d000 {
143+
compatible = "arm,coresight-etm3x", "arm,primecell";
144+
reg = <0x5414d000 0x1000>;
145+
ti,hwmods = "l3_main_3", "l3_instr", "debugss";
146+
147+
clocks = <&trace_clk_div_ck>;
148+
clock-names = "apb_pclk";
149+
cpu = <&CPU1>;
150+
port {
151+
ptm1_out_port: endpoint {
152+
remote-endpoint = <&mpu_funnel_in_port1>;
153+
};
154+
};
155+
};
156+
157+
funnel@54158000 {
158+
compatible = "arm,coresight-funnel", "arm,primecell";
159+
reg = <0x54158000 0x1000>;
160+
ti,hwmods = "l3_main_3", "l3_instr", "debugss";
161+
162+
clocks = <&trace_clk_div_ck>;
163+
clock-names = "apb_pclk";
164+
ports {
165+
#address-cells = <1>;
166+
#size-cells = <0>;
167+
168+
/* funnel output ports */
169+
port@0 {
170+
reg = <0>;
171+
mpu_funnel_out_port: endpoint {
172+
remote-endpoint =
173+
<&replicator_in_port>;
174+
};
175+
};
176+
177+
/* funnel input ports */
178+
port@1 {
179+
reg = <0>;
180+
mpu_funnel_in_port0: endpoint {
181+
slave-mode;
182+
remote-endpoint = <&ptm0_out_port>;
183+
};
184+
};
185+
186+
port@2 {
187+
reg = <1>;
188+
mpu_funnel_in_port1: endpoint {
189+
slave-mode;
190+
remote-endpoint = <&ptm1_out_port>;
191+
};
192+
};
193+
};
194+
};
195+
196+
replicator {
197+
compatible = "arm,coresight-replicator";
198+
clocks = <&trace_clk_div_ck>;
199+
clock-names = "apb_pclk";
200+
ti,hwmods = "l3_main_3", "l3_instr", "debugss";
201+
202+
ports {
203+
#address-cells = <1>;
204+
#size-cells = <0>;
205+
206+
/* replicator output ports */
207+
port@0 {
208+
reg = <0>;
209+
replicator_out_port0: endpoint {
210+
remote-endpoint = <&tpiu_in_port>;
211+
};
212+
};
213+
port@1 {
214+
reg = <1>;
215+
replicator_out_port1: endpoint {
216+
remote-endpoint = <&dbg_funnel_in_port0>;
217+
};
218+
};
219+
220+
/* replicator input port */
221+
port@2 {
222+
reg = <0>;
223+
replicator_in_port: endpoint {
224+
slave-mode;
225+
remote-endpoint = <&mpu_funnel_out_port>;
226+
};
227+
};
228+
};
229+
};
230+
231+
funnel@54164000 {
232+
compatible = "arm,coresight-funnel", "arm,primecell";
233+
reg = <0x54164000 0x1000>;
234+
ti,hwmods = "l3_main_3", "l3_instr", "debugss";
235+
236+
clocks = <&trace_clk_div_ck>;
237+
clock-names = "apb_pclk";
238+
ports {
239+
#address-cells = <1>;
240+
#size-cells = <0>;
241+
242+
/* funnel output ports */
243+
port@0 {
244+
reg = <0>;
245+
dbg_funnel_out_port: endpoint {
246+
remote-endpoint =
247+
<&etb_in_port>;
248+
};
249+
};
250+
251+
/* funnel input ports */
252+
port@1 {
253+
reg = <0>;
254+
dbg_funnel_in_port0: endpoint {
255+
slave-mode;
256+
remote-endpoint = <&replicator_out_port1>;
257+
};
258+
};
259+
260+
/*
261+
port@2 {
262+
reg = <1>;
263+
dbg_funnel_in_port1: endpoint {
264+
slave-mode;
265+
remote-endpoint = <&ptm1_out_port>;
266+
};
267+
};
268+
*/
269+
};
270+
};
271+
272+
etb@54162000 {
273+
compatible = "arm,coresight-etb10", "arm,primecell";
274+
reg = <0x54162000 0x1000>;
275+
ti,hwmods = "l3_main_3", "l3_instr", "debugss";
276+
277+
clocks = <&trace_clk_div_ck>;
278+
clock-names = "apb_pclk";
279+
port {
280+
etb_in_port: endpoint {
281+
slave-mode;
282+
remote-endpoint = <&dbg_funnel_out_port>;
283+
};
284+
};
285+
};
286+
287+
tpiu@54163000 {
288+
compatible = "arm,coresight-tpiu", "arm,primecell";
289+
reg = <0x54163000 0x1000>;
290+
ti,hwmods = "l3_main_3", "l3_instr", "debugss";
291+
292+
clocks = <&trace_clk_div_ck>;
293+
clock-names = "apb_pclk";
294+
port {
295+
tpiu_in_port: endpoint {
296+
slave-mode;
297+
remote-endpoint = <&replicator_out_port0>;
298+
};
299+
};
300+
};
301+
127302
l4_cfg: l4@4a000000 {
128303
compatible = "ti,omap4-l4-cfg", "simple-bus";
129304
#address-cells = <1>;

‎arch/arm/mach-omap2/io.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -416,6 +416,7 @@ static void __init omap_hwmod_init_postsetup(void)
416416
/* Set the default postsetup state for all hwmods */
417417
#ifdef CONFIG_PM
418418
postsetup_state = _HWMOD_STATE_IDLE;
419+
postsetup_state = _HWMOD_STATE_ENABLED;
419420
#else
420421
postsetup_state = _HWMOD_STATE_ENABLED;
421422
#endif

‎arch/arm/mach-omap2/omap_hwmod.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2097,9 +2097,9 @@ static int _enable(struct omap_hwmod *oh)
20972097
if (oh->_state != _HWMOD_STATE_INITIALIZED &&
20982098
oh->_state != _HWMOD_STATE_IDLE &&
20992099
oh->_state != _HWMOD_STATE_DISABLED) {
2100-
WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n",
2101-
oh->name);
2102-
return -EINVAL;
2100+
// WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n",
2101+
// oh->name);
2102+
return 0;
21032103
}
21042104

21052105
/*

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