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Reading Kaguya
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Reading Kaguya
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Pinned Loading

  1. RiscV_OoO_Processor RiscV_OoO_Processor Public

    And out of order processor project following the University of Michigan EECS 470 Coursework, from start to finish

    SystemVerilog

  2. RiscV_InOrder_Pipelined_CPU RiscV_InOrder_Pipelined_CPU Public

    RiscV In-order Pipe-lined Processor that utilizes a completely free and accessible toolchain for testing

    SystemVerilog

  3. FMC424-I2C-Controller FMC424-I2C-Controller Public

    I2C controller to perform required functions to integrate, monitor and utilize FMC424 Dual QSFP+ Vita 57.1 Compliant Mezzanine Board

    SystemVerilog

  4. Compilers_Final Compilers_Final Public

    OCaml