Ben Eaters 8-bit CPU

I made this project (in Summer 2020 (Covid Year)) to teach myself

Architectural Features

• Really simple design
• 16 byte RAM
• 2 8-bit Register (A, B)
• Single 8-bit Bus
• 8-bit output
• Multi-Cycle Design
• Von-Neumann Architecture
• Easily customizable instruction set (microcode_rom.v)
• Turing-Complete (with the default instruction set)

Tested on

• DE10-Lite FPGA Board (Terasic)

"Default Stages"

• Fetch (2 cycles)
• Execute (1-6 cycles)

Origin

https://eater.net/8bit