CPC Sixrom Card
This project is a CPLD-based ROM expansion board. Although only 3 sockets are provided each can be filled with a 'double size' EEPROM to provide the equivalent of 6 classic 16KByte Amstrad ROMs.
The board will co-exist with other ROM cards and uses DIP switches to enable or disable ROMs individually and to select how the ROMs on the card will be numbered to avoid clashes with other cards.
One special feature of the board is that it can be used to replace the CPC 'lower' (firmware) ROM as well as the upper paged application ROMs. The most common use of this feature is to allow CPC464 users to load a 6128 ROM with firmware and BASIC 1.1. Other lower ROMs for system diagnostics are available, e.g. Gerald's RAM test, as well as boot ROMs for alternative OSes or patched versions of the CPC originals.
Each ROM socket can take
- a 2764 8K EPROM
- a 27128 16K EPROM (the classic AMSTRAD ROM size)
- a 28C256 32K EEPROM
- a 27256 32K EPROM
- a 27SF256 32K Flash EPROM
DIP switches 1-6 are used to enable ROMs according to the following table
| DIP Switch | ON |
|---|---|
| 1 | enable lower ROM SKT01 |
| 2 | enable upper ROM SKT01 |
| 3 | enable lower ROM SKT23 |
| 4 | enable upper ROM SKT23 |
| 5 | enable lower ROM SKT45 |
| 6 | enable upper ROM SKT45 |
DIP switches 7-8 select the ROM numbers to be assigned to each socket as follows
| DIP8 | DIP7 | SKT01 | SKT23 | SKT45 | Comment |
|---|---|---|---|---|---|
| OFF | OFF | Lower ROM, ROM 0 [BASIC] | ROM 1, ROM 2 | ROM 3, ROM 4 | Lower ROM and BASIC replacement and first ROM bank |
| OFF | ON | Lower ROM, ROM 0 | ROM 10, ROM 11 | ROM 12, ROM 13 | FutureOS ROM configuration with optional FOS Boot ROM in Lower ROM position (or Lower ROM/BASIC replacement) |
| ON | OFF | ROM 1, ROM 2 | ROM 3, ROM 4 | ROM 5, ROM 6 | ROMs 1-6 in first ROM bank, no lower ROM or Firmware replacement |
| ON | ON | ROM 8, ROM 9 | ROM 10, ROM 11 | ROM 12, ROM 13 | ROMs 8-13 in second ROM bank, still FOS compatible |
Although the 28xxx series and 27xxx series are otherwise fully compatible, there is a minor difference in pinout which places the most significant address bit of the EPROM types onto the Write Enable pin of the EEPROMs. The updated V1.10 board places a 2 pin link next to each ROM socket. When using an EEPROM in the socket, leave the two pins of the link open. When using an 27xxx EPROM, use a jumper header to bridge the two pins.
(On the older V1.00 Card, only half of a 27256 EPROM can be used because of the pinout differences described above. So, these parts can be used to hold one classic ROM which is usually programmed in both upper and lower halves of the IC. The DIP switches should be set then to enable only the upper half.)
| Component | Function | Item | Value | Qty | Alternative Part |
|---|---|---|---|---|---|
| R10K_0-2 | Pull-up | Resistor | 10K 1/4W | 3 | Any resistor between ~3K3 and 50K |
| LK0-2 | Link pins | PCB Pins | 2 | 3 | |
| LK0-2 | Link header | Jumper Header | - | 3 | |
| ROM01,23,45 | ROM sockets | DIL Socket | 28W | 3 | |
| JTAG | CPLD programming con. | PCB Pins | 4x2 | 1 | |
| SIL0 | Pull-ups | Resistor Array 9 Pin | 10K | 1 | Any SIL resistors between ~3K3 and 50K |
| DIPSW0 | Mode selection | DIP Switch | 8 Way | 1 | |
| C100N_1-6 | Decoupling | Capacitor | 100nF | 6 | |
| CPLD | CPLD Socket | PLCC Socket | 44 Pin | 1 | |
| CPLD | CPLD | Xilinx XC9536 | PLCC 44 | 1 | Xilinx XC9572-PC44 |
| CONN1 | MX4 Header Connector | R/A Rect. Male Con. | 50W | 1 | |
| D0 | RAMDIS connection | Signal Diode | 1N4148 | 1 | 1N4007 |
| C22UF | Board decoupling | Electrolytic Cap. | 22uF | 1 |
All programs and data files in this project are made available under the terms of the GNU General Public License v3.
