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This does work on ARM? #6
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Hmm, it seems that changing the Aha, but! I uses other instructions, such as |
There's actually a paper from Hans Boehm showing that you cannot express
Seqlock in C++11 memory model :(.
I would recommend making your own version that uses assembly to insert to
correct memory barriers.
…On Fri, Feb 10, 2023 at 5:28 AM Martijn Courteaux ***@***.***> wrote:
Hmm, it seems that changing the -mcpu=cortex-m3 to -mcpu=cortex-a76
removes the dmb instructions...
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The count.fetch_add(0) recommended by that paper is actually recognized by clang - on x64 it compiles to an mfence followed by a regular load. gcc doesn't do this, however. Best bet might be count.fetch_add(0) as a default with a manual mfence+load for platforms known to need it (e.g. gcc x64). Then at least you know the ordering will be correct even if it doesn't perform optimally everywhere. |
Fascinating. I’d do a couple of lines of inline asm, or use intrinsics and plain C and be sure. I know intrinsics aren’t very portable but that’s one of those cases where correctness and performance prevail over portability. Just my 0.02ct |
Yes and unfortunately it's not really possible to implement seqlock in
C++11 :(
…On Thu, Mar 2, 2023 at 12:52 AM stravager ***@***.***> wrote:
axelriet the whole point of this repo is to portable though. It's supposed
to be a generic C++11 seqlock.
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Reading your README says that you "need to generate a
dmb
instruction on ARM, which is impossible in C++11". That sounds strange to me as the C++ language memory model should always just correctly follow the "as if" rule, regardless of the hardware.Testing this on Godbolt seems to indeed generate quite some
dmb ish
instructions:https://godbolt.org/z/93oha5Mn3
So, what's going on with the claim in the README? Are you saying that this seqlock implementation is incorrect with respect to the language memory model, but just happens to work on the x86-TSO memory model?
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