Move virtual 'prv' register to a seperate section to make it more cle…

…ar it is not a real register.
riscv · May 6, 2017 · 0512f5d · 0512f5d
1 parent 6b3c9d7
commit 0512f5d
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diff --git a/Makefile b/Makefile
@@ -9,6 +9,7 @@ REGISTERS_TEX += dm_registers.tex
 REGISTERS_TEX += trace_registers.tex
 REGISTERS_TEX += sample_registers.tex
 REGISTERS_TEX += abstract_commands.tex
+REGISTERS_TEX += sw_registers.tex
 
 REGISTERS_CHISEL += dm_registers.scala
 REGISTERS_CHISEL += abstract_commands.scala

diff --git a/core_debug.tex b/core_debug.tex
@@ -49,3 +49,10 @@ \section{Core Debug Registers} \label{debreg}
 The Core Debug Registers must be implemented for each hart being debugged.
 
 \input{core_registers.tex}
+
+\section{Virtual Debug Registers} \label{virtreg}
+
+Virtual debug registers are a requirement on the debugger SW/interface,
+not on the Core designer.
+
+\input{sw_registers.tex}
diff --git a/riscv-debug-spec.tex b/riscv-debug-spec.tex
@@ -43,6 +43,7 @@
 \input{trace_registers.tex.inc}
 \input{sample_registers.tex.inc}
 \input{abstract_commands.tex.inc}
+\input{sw_registers.tex.inc}
 
 \input{vc.tex}