Always order interrupt priority by privilege mode

https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/_SECLWl8qWk
riscv · Aug 18, 2017 · a62e76c · a62e76c
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diff --git a/src/machine.tex b/src/machine.tex
@@ -1316,8 +1316,8 @@ \subsection{Machine Interrupt Registers ({\tt mip} and {\tt mie})}
 Multiple simultaneous interrupts destined for different privilege modes are
 handled in decreasing order of destined privilege mode.  Multiple simultaneous
 interrupts destined for the same privilege mode are handled in the following
-decreasing priority order: MEI, SEI, UEI, MSI, SSI, USI, MTI, STI,
-UTI.  Synchronous exceptions are of lower priority than all interrupts.
+decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, UEI, USI, UTI.
+Synchronous exceptions are of lower priority than all interrupts.
 
 \subsection{Machine Timer Registers ({\tt mtime} and {\tt mtimecmp})}
 

diff --git a/src/riscv-privileged.tex b/src/riscv-privileged.tex
@@ -38,9 +38,9 @@
 Christopher Celio, David Chisnall, Anthony Coulter, Palmer Dabbelt, Monte
 Dalrymple, Dennis Ferguson, Mike Frysinger, John Hauser, David Horner, Olof
 Johansson, Yunsup Lee, Andrew Lutomirski, Jonathan Neusch{\"a}fer, Rishiyur
-Nikhil, Stefan O'Rear, Albert Ou, John Ousterhout, David Patterson, Colin
-Schmidt, Wesley Terpstra, Matt Thomas, Tommy Thorn, Ray VanDeWalker, Megan
-Wachs, Andrew Waterman, and Reinoud Zandijk.
+Nikhil, Stefan O'Rear, Albert Ou, John Ousterhout, David Patterson, Dmitri
+Pavlov, Colin Schmidt, Wesley Terpstra, Matt Thomas, Tommy Thorn, Ray
+VanDeWalker, Megan Wachs, Andrew Waterman, and Reinoud Zandijk.
 
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 International License.