Simplify interrupt-stack discipline

h/t @jhauser-ucberkeley

src/machine.tex

@@ -487,7 +487,7 @@ \subsection{Privilege and Global Interrupt-Enable Stack in {\tt mstatus} registe
 fields can only hold privilege modes up to {\em x}, so MPP and HPP are
 two bits wide, SPP is one bit wide, and UPP is implicitly zero.  When
 a trap is taken from privilege mode {\em y} into privilege mode {\em
-  x}, {\em x}\,PIE is set to the value of {\em y}\,IE; {\em x}\,IE is set to
+  x}, {\em x}\,PIE is set to the value of {\em x}\,IE; {\em x}\,IE is set to
 0; and {\em x}\,PP is set to {\em y}.
 
 \begin{commentary}
@@ -502,7 +502,7 @@ \subsection{Privilege and Global Interrupt-Enable Stack in {\tt mstatus} registe
 The MRET, HRET, SRET, or URET instructions are used to return from
 traps in M-mode, H-mode, S-mode, or U-mode respectively.  When
 executing an {\em x}RET instruction, supposing {\em x}\,PP holds the
-value {\em y}, {\em y}\,IE is set to {\em x}\,PIE; the privilege mode
+value {\em y}, {\em x}\,IE is set to {\em x}\,PIE; the privilege mode
 is changed to {\em y}; {\em x}\,PIE is set to 1; and {\em x}\,PP is
 set to U (or M if user-mode is not supported).
 

src/priv-preface.tex

@@ -19,6 +19,7 @@ \chapter{Preface}
       set them.
 \item The counter-enable scheme has changed, so that H-mode and S-mode can
       control availability of counters to S-mode and U-mode, respectively.
+\item The interrupt-enable stack discipline has been simplified.
 \end{itemize}
 
 \section*{Preface to Version 1.9.1}

src/supervisor.tex

@@ -163,13 +163,10 @@ \subsection{Supervisor Status Register (\tt sstatus)}
 supervisor-level interrupts are enabled.  The supervisor can disable
 indivdual interrupt sources using the {\tt sie} register.
 
-The SPIE bit indicates whether interrupts were enabled before entering
-supervisor mode.  When a trap is taken into supervisor mode, SPIE is
-set to either SIE or UIE depending on whether the trap was taken in
-supervisor or user mode respectively, and SIE is set to 0.  When an
-SRET instruction is executed, if SPP=S, then SIE is set to SPIE; or
-if SPP=U, then UIE is set to SPIE.  In either case, SPIE is then set
-to 1.
+The SPIE bit indicates whether supervisor interrupts were enabled prior to
+trapping into supervisor mode.  When a trap is taken into supervisor
+mode, SPIE is set to SIE, and SIE is set to 0.  When an SRET instruction is
+executed, SIE is set to SPIE, then SPIE is set to 1.
 
 The UIE bit enables or disables user-mode interrupts.  User-level interrupts
 are enabled only if UIE is set and the hart is running in user-mode.  The UPIE