Made clear that vstart and vcsr are XLEN-bit wide registers.

v-spec.adoc

@@ -29,6 +29,8 @@ Alex Solomatnikov, Steve Wallach, Andrew Waterman, Jim Wilson.
 
 === Make encodings reserved if the same vector register would be read with two or more different EEWs by the same instruction.
 
+=== Made clear that `vstart` and `vcsr` are XLEN-bit wide registers.
+
 :sectnums:
 
 == Introduction
@@ -527,9 +529,9 @@ settings which require them to be saved and restored.
 
 === Vector Start Index CSR `vstart`
 
-The `vstart` read-write CSR specifies the index of the first element
-to be executed by a vector instruction, as described in Section
-<<sec-inactive-defs>>.
+The _XLEN_-bit-wide read-write `vstart` CSR specifies the index of the
+first element to be executed by a vector instruction, as described in
+Section <<sec-inactive-defs>>.
 
 Normally, `vstart` is only written by hardware on a trap on a vector
 instruction, with the `vstart` value representing the element on which
@@ -643,15 +645,15 @@ The `vxsat` bit is mirrored in `vcsr`.
 === Vector Control and Status Register `vcsr`
 
 The `vxrm` and `vxsat` separate CSRs can also be accessed via fields
-in the vector control and status CSR, `vcsr`.
+in the _XLEN_-bit-wide vector control and status CSR, `vcsr`.
 
 .vcsr layout
 [cols=">2,4,10"]
 [%autowidth]
 |===
 | Bits | Name   | Description
 
-
+| XLEN-1:3 |       | Reserved
 |  2:1 | vxrm[1:0] | Fixed-point rounding mode
 |    0 | vxsat     | Fixed-point accrued saturation flag
 |===