Adds a new vcsr CSR that includes vxrm,vxsat but also the two

floating-point fields fflags and ffrm.  Provides a cleaner design that
having fields in fcsr, in particular, avoiding adding fcsr when no FPU
in system, or when disabling FPU using VS.
Closes #341.

v-spec.adoc

@@ -90,11 +90,9 @@ or SLEN parameters.
 
 == Vector Extension Programmer's Model
 
-The vector extension adds 32 vector registers, and six unprivileged
-CSRs (`vstart`, `vxsat`, `vxrm`, `vtype`, `vl`, `vlenb`) to a base scalar
-RISC-V ISA.  If the base scalar ISA does not include floating-point,
-then a `fcsr` register is also added to hold mirrors of the `vxsat`
-and `vxrm` CSRs as explained below.
+The vector extension adds 32 vector registers, and seven unprivileged
+CSRs (`vstart`, `vxsat`, `vxrm`, `vcsr`, `vtype`, `vl`, `vlenb`) to a
+base scalar RISC-V ISA.
 
 .New vector CSRs
 [cols="2,2,2,10"]
@@ -105,6 +103,7 @@ and `vxrm` CSRs as explained below.
 | 0x008 | URW | vstart | Vector start position
 | 0x009 | URW | vxsat  | Fixed-Point Saturate Flag
 | 0x00A | URW | vxrm   | Fixed-Point Rounding Mode
+| 0x00F | URW | vcsr   | Vector control and status register
 | 0xC20 | URO | vl     | Vector length
 | 0xC21 | URO | vtype  | Vector data type register
 | 0xC22 | URO | vlenb  | VLEN/8 (vector register length in bytes)
@@ -119,7 +118,7 @@ Each vector register has a fixed VLEN bits of state.
 
 NOTE: Zfinx ("F in X") is a new ISA option under consideration where
 floating-point instructions take their arguments from the integer
-register file.  The 0.8 vector extension is also compatible with this
+register file.  The 0.9 vector extension is also compatible with this
 option.
 
 === Vector Context Status in `mstatus`
@@ -128,35 +127,34 @@ A vector context status field, `VS`, is added to `mstatus[24:23]` and shadowed
 in `sstatus[24:23]`.  It is defined analogously to the floating-point context
 status field, `FS`.
 
-Attempts to execute any vector instruction, or to access the `vl`,
-`vtype`, `vlenb`, or `vstart` CSRs, raise an illegal-instruction
-exception when the `VS` field is set to Off.
+Attempts to execute any vector instruction, or to access the vector
+CSRs, raise an illegal-instruction exception when the `VS` field is
+set to Off.
 
 When the `VS` field is set to Initial or Clean, executing any
-instruction that changes vector state, including the `vl`, `vtype`,
-and `vstart` registers, will change `VS` to Dirty.
+instruction that changes vector state, including the vector CSRs, will
+change `VS` to Dirty.
 
 NOTE: Implementations may also change `VS` field to Dirty at any time,
 even when there is no change in vector state.  Accurate setting of the
 `VS` field is an optimization.
 
-Attempts to access an `f` register or the `fcsr`, `vxsat`, or `vxrm` CSRs raise an
-illegal-instruction exception when the floating-point context status `FS` is
-set to Off.
-
-NOTE: Vector instructions that read or write an `f` register or `fcsr`, `vxsat`, or `vxrm` raise
-an illegal-instruction exception if either `VS` or `FS` is set to Off.
-However, these CSRs can be read or written using CSR-access instructions when
-`FS` is set to a value other than Off, irrespective of the value of `VS`.
+When the floating-point context status `FS` is set to Off, attempts to
+access an `f` register or the `fcsr` CSR raise an illegal-instruction
+exception.  All vector floating-point instructions will also raise an
+illegal instruction exception if `FS` is set to Off.
 
-If `FS` is set to Initial or Clean, executing any instruction that changes
-`fcsr`, `vxsat`, `vxrm`, or an `f` register will change `FS` to Dirty.
+NOTE: Even vector-vector floating-point instructions that do not
+access the `f` registers need to read the dynamic rounding mode in
+`frm` and might need to raise an exception flag in `fflags` and so
+cannot be executed when FS is set to Off.
 
-NOTE: Context-switching code must save all of `fcsr` if `FS` is set to Dirty.
+If `FS` is set to Initial or Clean, executing any vector instruction
+that changes `fflags` or an `f` register will change `FS` to Dirty.
 
-NOTE: Fixed-point-only implementations, which would not benefit from lazy
-floating-point save/restore, might hardwire the `FS` field to Dirty to
-reduce cost.  In this case, `fcsr` would always be accessible.
+NOTE: Implementations may conservatively change `FS` to Dirty even if
+executing the vector instruction does not actually change the value in
+`fflags` or the `f` register.
 
 === Vector type register, `vtype`
 
@@ -392,9 +390,7 @@ a vector arithmetic instruction when `vstart` is nonzero.
 The vector fixed-point rounding-mode register holds a two-bit
 read-write rounding-mode field.  The vector fixed-point rounding-mode
 is given a separate CSR address to allow independent access, but is
-also reflected as a field in the upper bits of `fcsr`.  Systems
-without floating-point must add `fcsr` when adding the vector
-extension.
+also reflected as a field in the upper bits of `vcsr`.
 
 The fixed-point rounding algorithm is specified as follows.
 Suppose the pre-rounding result is `v`, and `d` bits of that result are to be
@@ -431,15 +427,16 @@ The `vxsat` CSR holds a single read-write bit that indicates if a
 fixed-point instruction has had to saturate an output value to fit
 into a destination format.
 
-The `vxsat` bit is mirrored in the upper bits of `fcsr`.
+The `vxsat` bit is mirrored in the upper bits of `vcsr`.
 
-=== Vector Fixed-Point Fields in `fcsr`
+=== Vector Control and Status Register `vcsr`
 
 The `vxrm` and `vxsat` separate CSRs can also be accessed via fields
-in the floating-point CSR, `fcsr`.  The `fcsr` register must be added
-to systems without floating-point that add a vector extension.
+in the vector control and status CSR, `vcsr`.  To reduce
+context-switch overhead, the `frm` and `fflags` CSRs are also mapped
+into `vcsr` at the same locations as in `fcsr`.
 
-.fcsr layout
+.vcsr layout
 [cols=">2,4,10"]
 [%autowidth]
 |===
@@ -452,8 +449,9 @@ to systems without floating-point that add a vector extension.
 |  4:0 | fflags | Floating-point accrued exception flags
 |===
 
-NOTE: The fields are packed into `fcsr` to make context-save/restore
-faster.
+When the floating-point unit is not present or is disabled
+(`*status.FS`=Off), the `frm` and `fflags` fields return zero when
+read, and writes to these fields are ignored.
 
 === State of Vector Extension at Reset