Propeller II

The next generation of the Propeller chip is currently under development by Parallax. It will undoubtedly be called something featuring the word "Propeller" at release. For now we refer to it as the Propeller 2. Nothing is certain about this chip so far, but Parallax has told the community about a lot of features they are expecting to include.

Early on they had talked about going with 16 COGs, but due to silicon size and other considerations they have gone back to 8. This may change, or they might do another version later with 16.

The primary values that seem to be settled on for now are 8 COGs, 128K Hub RAM (tentatively Beau Schwabe has said 256K is still a possibility), 32K ROM, 92 I/Os, and 160Mhz.

Here is a page with information about proposed: Propeller 2 Instructions.

Here is a link to the Propeller 2 feature list released by Parallax: Propeller 2 Feature List

Features mentioned in posts on the parallax forums:

Feature	Quantity	Comments	Forum post link
Cogs	8 v	COG instructions pipelined (1 per clock effective)
Hub instructions take 2 clocks, you can fit 6 regular instructions between successive hub accesses.
Quad-long read (four longs in one hub instruction) is on the slate for implementation as well	8 COGs post (other mentions in the newer posts from Aug 2008 to Sept 2008)
Other data: Chip post
		HUB access every 8 clocks	Chip post
		512 longs per COG (same number, but more will be available for coding than the Prop 1, 506 vs 496)	Chip post
		256 entry 16bit CLUT, used with VSU to get 16bit color data per pixel. Also accessible as 128 longs of general storage.
"The CLUT will not be rewritten during a cog reload, so it will retain its prior contents."	Chip post

Chip post | | Memory | RAM 128K v | HUB memory Layout Engineer Beau Schwabe assures room on the die for at 128K, and some rearranging may allow for 256K. | Beau Post | | | ROM 32K v | ROM includes entire development system. (No need for PC!) Released info from Parallax says 32K. | 128k ROM: Chip post Other: Chip post | | HUB Address Space | 32bit v | In order to have 128KB RAM and 32KB ROM, they had to expand. They decided to go all the way to 32bit. | Chip post | | I/Os | 92 v | Most recent posts say it's 92 now.

"each pair of adjacent Prop II I/Os has a high-speed comparator between them that can toggle at 50MHz" | Chip post Chip post

Chip post | | ADC/DAC | 92 v | "EVERY pin will have one these babies in it, along with a comparator, a delta-sigma ADC, a delta-sigma DAC, a high speed signal/video 75-ohm DAC, pull-ups/downs, slew control, float/weak/strong HIGH/LOW combos, schmitt input w/feedback, crystal oscillator, and a few other things" | Chip post | | Serializer / Deserializer | ? | "I just need to narrow down what kinds of demodulation we should support. Manchester and NRZ come to mind" | Chip post | | PLL speed | 160Mhz ? | They hope to reach 160Mhz. | Chip post | | Packaging | | TQFP-128 (14x14mm) ? QFN-128 (12x12mm) ? | Chip post Chip post | | Process | 180nm v | | Beau post | | Pins | 128 | 92 I/Os v 8 VP0-7 power 1 per 8 I/Os (1.8v - 3.3v) (more functional at 3.3v) v 8 GP0-7 grounds 1 per 8 I/Os v 8 VDD 1.8v Core power v 8 GND v 1 RESn Reset v 2 XI/XO Clock v 1 BOEn Brown Out v | VIO pins: Chip post

Pin arrangement Image from Beau: Image |

legend: ? = not yet defined by Parallax | v = mentioned by Parallax (Chip, Paul, Beau)

The information on this page and the Propeller 2 Instructions page was gathered primarily from the following posts:

• What would you want more of, cogs or RAM? (started 24Nov06)
• More Prop II info..!?! (started 21Aug08)
• Should the next Propeller be code-compatible? (started 27Aug08)
• Prop II on-chip development question (started 22Nov09)