- 👋 Hi, I’m @rpjayaraman
- 👀 I’m interested in Hardware
- 🌱 I’m working as an ASIC DV Engineer
- 📫 How to reach me jrp.postbox@gmail.com
Popular repositories Loading
-
RISCV_CPU_DESIGN-rpjayaraman
RISCV_CPU_DESIGN-rpjayaraman PublicForked from RISCV-MYTH-WORKSHOP/RISCV_CPU_DESIGN-rpjayaraman
riscv_myth_workshop_nov22-rpjayaraman created by GitHub Classroom
-
-
-
CTB_2022-Hackathon
CTB_2022-Hackathon PublicForked from vyomasystems-lab/challenges-rpjayaraman
challenges-rpjayaraman created by GitHub Classroom
Verilog
-
vw_SVunit_verilator
vw_SVunit_verilator PublicForked from verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
C++
-
svunit_verilator
svunit_verilator PublicForked from svunit/svunit
Reference form Srini: https://github.com/svenka3/svunit/tree/srini_verilator
SystemVerilog
If the problem persists, check the GitHub status page or contact support.