Merge pull request #14 from dron0gus/qspi-flash

Qspi flash
rusefi · Aug 16, 2021 · 8c8b39d · 8c8b39d
2 parents dfda1a8 + 18d5a96
commit 8c8b39d
Show file tree

Hide file tree

Showing 3 changed files with 13 additions and 4 deletions.
diff --git a/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.c b/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.c
@@ -270,17 +270,17 @@ static void n25q_reset_memory(SNORDriver *devp) {
 #else
   /* 2x N25Q_CMD_RESET_ENABLE command.*/
   static const wspi_command_t cmd_reset_enable_2 = {
-    .cfg              = WSPI_CFG_CMD(N25Q_CMD_RESET_ENABLE) |
-                        WSPI_CFG_CMD_MODE_TWO_LINES,
+    .cmd              = N25Q_CMD_RESET_ENABLE,
+    .cfg              = WSPI_CFG_CMD_MODE_TWO_LINES,
     .addr             = 0,
     .alt              = 0,
     .dummy            = 0
   };
 
   /* 2x N25Q_CMD_RESET_MEMORY command.*/
   static const wspi_command_t cmd_reset_memory_2 = {
-    .cfg              = WSPI_CFG_CMD(N25Q_CMD_RESET_MEMORY) |
-                        WSPI_CFG_CMD_MODE_TWO_LINES,
+    .cmd              = N25Q_CMD_RESET_MEMORY,
+    .cfg              = WSPI_CFG_CMD_MODE_TWO_LINES,
     .addr             = 0,
     .alt              = 0,
     .dummy            = 0

diff --git a/os/hal/lib/complex/serial_nor/hal_serial_nor.h b/os/hal/lib/complex/serial_nor/hal_serial_nor.h
@@ -156,8 +156,10 @@ typedef struct {
 #ifdef __cplusplus
 extern "C" {
 #endif
+#if SNOR_SHARED_BUS == TRUE
   void bus_acquire(BUSDriver *busp, const BUSConfig *config);
   void bus_release(BUSDriver *busp);
+#endif
   void bus_cmd(BUSDriver *busp, uint32_t cmd);
   void bus_cmd_send(BUSDriver *busp, uint32_t cmd, size_t n, const uint8_t *p);
   void bus_cmd_receive(BUSDriver *busp,

diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c
@@ -95,13 +95,20 @@ static void wspi_lld_serve_interrupt(WSPIDriver *wspip) {
   while (dmaStreamGetTransactionSize(wspip->dma) > 0U)
     ;
 
+  /* Clearing DMA interrupts here because the DMA ISR is not called on
+     transfer complete.*/
+  dmaStreamClearInterrupt(wspip->dma);
+
+#if defined(STM32L471xx) || defined(STM32L475xx) ||                         \
+    defined(STM32L476xx) || defined(STM32L486xx)
   /* Handling of errata: Extra data written in the FIFO at the end of a
      read transfer.*/
   if (wspip->state == WSPI_RECEIVE) {
     while ((wspip->qspi->SR & QUADSPI_SR_BUSY) != 0U) {
       (void) wspip->qspi->DR;
     }
   }
+#endif
 }
 
 /*===========================================================================*/