Add STIR register to NVIC peripheral #91
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Thanks for the PR, @thenewwazoo.
I left comments about few things that need / should be changed.
Could you also add a test in peripheral/test.rs that checks that STIR has address 0xE000EF00?
| reserved5: [u32; 696], | ||
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| /// Software Trigger Interrupt | ||
| pub stir: WO<u32>, |
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STIR is not present on ARMv6-M so this needs #[cfg(not(armv6m))].
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| impl NVIC { | ||
| /// Request an IRQ in software | ||
| pub fn req_irq<I>(&mut self, interrupt: I) |
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I think this method should be renamed to request. The other NVIC methods like enabled(interrupt: I) are read as "enable interrupt", so I think "request interrupt" would be more fitting.
I think this method should include a comment similar to what's included in the ARM documentation:
Writing a value to the INTID field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register.
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I think this method should include a comment similar to what's included in the ARM documentation:
in particular the comment should mention that this method is similar to set_pending.
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Thank you for this PR @thenewwazoo ! Unfortunately we haven't heard from you on this in a while, so I'm closing the PR to keep things tidy. Don't worry though, if you'll have time again in the future please reopen this PR, we'll be happy to review it again! |
95: [RFC] remove build dependency on arm-none-eabi-gcc (binary blob alternative) r=japaric a=japaric Before this commit we used gcc to assemble external assembly files into object files that we linked into our Rust program. This commit drops the dependency on gcc by shipping the already assembled object files with this crate source code. --- This is an alternative to RFC #91 that doesn't require a breaking change or adding a new Cargo feature and can be implemented right now. See #91 for the rationale of dropping the dependency on gcc. This approach can be applied to other Cortex-M crates like cortex-m-semihosting and cortex-m (would subsume RFC #107). This seems like an overall better approach to me, but before I go opening more PRs I want to hear your thoughts, @rust-embedded/cortex-m closes #91 Co-authored-by: Jorge Aparicio <jorge@japaric.io>
Quick and dirty PR to add software interrupt request capability