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SKW: Change memory interfaces to Wishbone style: #22

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ben-marshall opened this issue Jul 17, 2020 · 1 comment
Closed
3 tasks done

SKW: Change memory interfaces to Wishbone style: #22

ben-marshall opened this issue Jul 17, 2020 · 1 comment
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RTL Issue with the synthesisable RTL skywater Associated with project skywater. Verification/Testing Issue with the verification code or infrastructure.

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ben-marshall commented Jul 17, 2020 •
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Depends on:

  • None

Tasks:

  • Instruction memory interface.
  • Data memory interface.
  • Simulation / testbench memory interface models.

Notes:

  • req/gnt interface.
  • CPU always accepts responses instantly.
@ben-marshall ben-marshall mentioned this issue Jul 17, 2020
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@ben-marshall ben-marshall added skywater Associated with project skywater. RTL Issue with the synthesisable RTL Verification/Testing Issue with the verification code or infrastructure. labels Jul 17, 2020
@ben-marshall ben-marshall self-assigned this Jul 17, 2020
ben-marshall added a commit that referenced this issue Jul 23, 2020
@ben-marshall
skw: Change memory interfaces.
e1b999b 
Closes issue #22

rtl:

- Changed memory interfaces such that responses always appear in the
  cycle after a request is granted (pipelined wishbone style).

- Removed `_recv` and `_ack` signals from imem/dmem interfaces.

- Small performance regression in the front end. Need to see how to
  keep the fetch buffer full while looking ahead.

verif:

- Changed to verilator testbench memory agent signalling.

- Changes to RVFI environment to remove redundant signals and assumptions.

 On branch scarv/skywater/dev
 Your branch is ahead of 'origin/scarv/skywater/dev' by 2 commits.
   (use "git push" to publish your local commits)

 Changes to be committed:
	modified:   rtl/core/frv_core.sv
	modified:   rtl/core/frv_core_fetch_buffer.sv
	modified:   rtl/core/frv_pipeline.sv
	modified:   rtl/core/frv_pipeline_fetch.sv
	modified:   rtl/core/frv_pipeline_writeback.sv
	modified:   verif/rvfi/fi_fairness.sv
	modified:   verif/rvfi/rvfi_wrapper.sv
	modified:   verif/verilator/dut_wrapper.cpp
	modified:   verif/verilator/dut_wrapper.hpp
	modified:   verif/verilator/sram_agent.cpp
	modified:   verif/verilator/sram_agent.hpp

 Changes not staged for commit:
	modified:   external/embench-iot (modified content)
	modified:   external/riscv-formal (untracked content)
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Closed with e1b999b.

@ben-marshall ben-marshall mentioned this issue Aug 13, 2020
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RTL Issue with the synthesisable RTL skywater Associated with project skywater. Verification/Testing Issue with the verification code or infrastructure.
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