Do not disable counters when reading on aarch64 #32
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If the cycle counter is disabled during a read, the operation can be preempted and lose the count of cycles for the duration of the preemption. Signed-off-by: Curtis Millar <curtis.millar@data61.csiro.au>
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Should armv7 also be updated in the same way? |
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armv7 performs this check in the kernel using the API to execute a function in the kernel. As this is performed while the kernel lock is held and while interrupts are disabled, it cannot be preempted. |
Can you show me where, because from what I can see, it accesses the register directly from userlevel: https://github.com/seL4/seL4_libs/blob/master/libsel4bench/arch_include/arm/armv/armv7-a/sel4bench/armv/sel4bench.h#L91 |
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Not sure where I saw it. You're right, the issue is also an ARMv7. |
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any plans to merge this? |
If the cycle counter is disabled during a read, the operation can be preempted and lose the count of cycles for the duration of the preemption. Signed-off-by: Curtis Millar <curtis.millar@data61.csiro.au> GitOrigin-RevId: 707000b
If the cycle counter is disabled during a read, the operation can be preempted and lose the count of cycles for the duration of the preemption.