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out_mpsse_spi: Make half row hack optional. #72

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vifino opened this issue Jan 20, 2019 · 1 comment
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out_mpsse_spi: Make half row hack optional. #72

vifino opened this issue Jan 20, 2019 · 1 comment
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enhancement Enhancement suggestions to the project.

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vifino commented Jan 20, 2019

Since most of the time, we don't need to go to the absolute maximum the iCEbreaker can give driving a HUB75 panel using @smunaut's rgb-panel Verilog code, the half row hack to save BRAM is not necessary.

So, add an option to make it optional.
@vifino vifino added the enhancement Enhancement suggestions to the project. label Jan 20, 2019
@vifino vifino self-assigned this Jan 20, 2019
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vifino commented Jan 21, 2019

Fixed as of #73, just set linediv=2,linepad=256 for the half row hack plus sync padding.

@vifino vifino closed this as completed Jan 21, 2019
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