Locate IO srst_n to proper pin on LCD connector #136
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LGTM, I will close https://github.com/sifive/fpga-shells/pull/130/files (Was waiting to hear from Yann if this solved his problem before I merged |
erikdanie
approved these changes
Jun 25, 2020
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This PR applies a location constraint and pullup to the srst_n input in VC707 builds. I know VC707 is not officially supported any more, but some engineers still have them and it's useful to be able to do internal builds targeted at VC707. Before this change, Vivado would error out because this I/O is in the design but it doesn't have a location constraint.
With this change, I was able to successfully build standard core U77 for VC707 using PCS.