Kasli v1.0 tests & errata #349

marmeladapk · 2017-11-06T17:11:41Z

To be changed for rev1.1

Misc:
- R57 must be 300R
- Improve signal integrity for backplane LVDS lines (remove reference plane cut) (one cut between 2v5 and 12V0 seems unavoidable)
- Add two more USER_LEDs
- (v1.1/rj) consider adding a PCB-mount heatsink (one of the FPGAs died from overheating
  during testing)
- Document power supply design parameters (Kasli dc/dc documentation #317)
- update
- and double check power budget after changes.
- add a PN for that clock balun on the schematic
- Change revision to 1.1 on schematics
USB:
- (v1.1/rj) Swap I2C with UART on FTDI chip (channel C doesn't have MPSSE)
- (v1.1/rj) fix direction of the IC19 (both channels)
I2C:
- (v1.1/rj) add TVS on EEM I2C
- (v1.1/rj) add ID chip 24AA02E48T-I/OT, same I2C port as the Si5324
- (v1.1/rj) Connect reset of the I2C routers IC14 IC15 to the FPGA
- Add TCA9517 to Si5324 I2C
- Connect IC10:A1 (I2C_SW_RESET) to one of the unused BDBUS lines (BDBUS7 or BDBUS5 if you can) and not to CDBUS4.
Backplane:
- (v1.1/rj) Inconsistent power connector PN 712RA vs L712RA (712RA is the correct one) (it was just wrong footprint name, PN was correct; PK)
- (v1.1/rj) Remove second power connector J17.
- (v1.1/rj) Populate the backplane connector J20.
SFP:
- Move SFP LEDs closer to panel (same as was done with USB)
- Free up six pins on the FPGA by having MOD_DEF1 and MOD_DEF2 routed through the I2C switch only and not additionally directly to the FPGA.
- Remove the I2C level converters IC10 on those SFP I2C busses.
- (v1.1/rj) Connect RATE_SELECT1 (pin 9 of the SFP) to the FPGA
Clock distribution
- (v1.1/rj) Remove the 50 MHz oscillator OSC1. Not needed as the 125 MHz GTP input can be routed to fabric.
- (v1.1/rj) Remove IC3
- Remove the CLK_SEL logic of IC3 (free up FPGA pin)
- (v1.1/rj) Remove J19 and related components
- (v1.1/rj) Remove J5-J7 and related components
- Remove the R98 path of CLK_OUT (IC1:Q2 to the front panel SMA)
- (v1.1/rj) Add an LDO for the power supply of IC1 and IC2 (also worth adding a ferrite/inductor between the SMPS and the LDO to kill high-frequency spurs).
- (v1.1/rj) Connect four MMCX (J1-J4) to the Q2, Q2B, Q3, Q3B outputs of IC1
- (v1.1/rj) Mark J2 and J4 (on the negative Q2B and Q3B outputs) clearly on the PCB
- (v1.1/rj) Connect backplane clock CLK_EXT_P/N to CKOUT2+- of IC2
- (tph) change 0R resistor to 100k to float SMA clock input
- (tph) consider floating MMCX connector grounds in same way as SMAs (only if you have time!)
- Change the transformer TR1 to TC2-1TX+. No changes to layout. Footprint and package are compatible. But pinout is rotated 180 degrees.
- DNP C13, C9
Layout:
- Either teardrops everywhere or nowhere. Right now there are teardrops on roughly half the pins.
- Set up consistent rules
- Properly clean up polygons
- Don't do arcs where they are not needed.
- Remove weird teardrop on FTDI
- Connect PCB edge GND stitching vias to top and bottom GND pour. Stick with @gkasprow recommendation on via density.
- Check XADC connection to components
- Replace C49 with a 0R (connect VREFN to XADC_GND) to use internal reference (connected without jumper, PK)

jordens · 2017-12-05T11:16:20Z

@marmeladapk @gkasprow Is Kasli back from the board house?

gkasprow · 2017-12-05T21:19:28Z

Components are delivered, the PCBs were shipped yesterday. They will start assembly on Monday. It takes roughly 2 days.

hartytp · 2017-12-05T21:35:20Z

Wonderful! Really looking forward to seeing these!

gkasprow · 2017-12-15T15:55:23Z

Kasli photo:

gkasprow · 2017-12-15T15:57:28Z

Power supplies work well. It consumes 0.2A@12V
USB works as well. At least I see 4 serial ports under Windows.

That's all what I can do at home.

hartytp · 2017-12-15T16:29:45Z

Great!

jordens · 2017-12-15T16:33:58Z

Awesome!

gkasprow · 2017-12-18T13:02:50Z

Progress;
JTAG works,
FLASH programming and booting works. There is litle bug, R57must be 300R
I loaded design which causes 2.5V rail to switch off. With little help of external PSU it wakes up but the board takes 600mA and FPGA gets really hot.
Then we realised that it must be split termination that is switched on on all EEM LVDS lines because there are just ordinary registers attached so far.
And indeed, the construct below instantiates uncallibrated split impedance


-- LVDS bidir buffers
	eem0 : for I in 0 to 7 generate
		lvds_buf : IOBUFDS_INTERMDISABLE
			GENERIC MAP (
				DIFF_TERM         => "true",
				IBUF_LOW_PWR      => "true",
				IOSTANDARD        => "LVDS_25",
				USE_IBUFDISABLE   => "false")
			PORT MAP (
				O                 => eem0_I(I),
				IO                => eem0_p(I),
				IOB               => eem0_n(I),
				INTERMDISABLE     => eem0_term_dis(I),
				I                 => eem0_O(I),
				IBUFDISABLE       => '0',
				T                 => eem0_S(I) -- 3-state enable input, high=input, low=output
			);

gkasprow · 2017-12-18T13:21:08Z

clock distribution works as well

jordens · 2017-12-18T17:21:09Z

Great job @gkasprow and @marmeladapk.

gkasprow · 2017-12-18T18:59:26Z

@jordens The only remaining thing we need to test is Silabs, I2C distribution and EEMs itself. Hopefully we will ship it in Wednesday. We can ship it as it is tomorrow and play with remaining boards that will be delivered on Wednesday.

jordens · 2017-12-18T20:03:15Z

No need to rush it then. I'll be gone Friday until the 28th. You can time it so that it arrives on the 28th.

gkasprow · 2017-12-19T17:14:47Z

I2C and silabs chip also work.

gkasprow · 2017-12-19T17:16:09Z

UART works as well. I talk with FORTH CPU

marmeladapk · 2017-12-26T00:11:17Z

@jordens I removed arcs remark, because they were added on purpose - reducing spikes of current density. Same as with you last remark about polygons (believe me, Greg bugged me about this).

We need to switch UART with I2C on FTDI chip, because channel C doesn't have MPSSE. I made bitbang I2C using pyftdi which works (I can program Si5324 and I2C switches), but its timings are horrible.

SFP0 and SFP2 seem to work on 6,25 Gbps. There is a problem with SFP1 TX line. GTP PLL locks both on 125 MHz source (OSC2) and on 125 MHz signal from Si5324 (which had 125 MHz input on SMA).

marmeladapk · 2017-12-26T01:16:34Z

@jordens Also FPGA tends to get quite hot with termination enabled so please cool it with fans to avoid damage. Also, there is some kind of a problem with XADC, sometimes it shows all voltages = 0 V and temperature = 0 K.

hartytp · 2017-12-27T15:59:17Z

@jordens Also FPGA tends to get quite hot with termination enabled so please cool it with fans to avoid damage. Also, there is some kind of a problem with XADC, sometimes it shows all voltages = 0 V and temperature = 0 K.

Should we add a heat sink to the FPGA to help to avoid this? Maybe a nice PCB-mount one?

jordens · 2017-12-29T15:43:12Z

@marmeladapk Current density at a bend diverges with sharpness/mesh size in many Maxwell approximations. If you think you need an arc, that's most likely a simulation/algorithm artefact which does not correspond to reality. I'd be very surprised if there was a case on Kasli where an arc solves a problem that a pair of 45 degree bends does not solve. Both on polygons and on traces.

Ack the UART/I2C switch. Could you post the bitbang i2c code somewhere?

Don't worry about the XADC. Did you test the DDR RAM?

On the GTP pairs you need to be a bit more careful with your design rules. You have some lines coupled closer to unrelated signals than to their differential pair partner!

jordens · 2017-12-29T17:25:27Z

@marmeladapk can't get jtag over usb to work. are DIR1 and DIR2 of IC19 wrong?

jordens · 2017-12-29T18:03:45Z

Either teardrops everywhere or nowhere. Right now there are teardrops on roughly half the pins.

Set up consistent rules

Properly clean up polygons

Don't do arcs where they are not needed.![image](https://user-images.githubusercontent.com/1338946/33930833-807e48f6-dfee-11e7-8665-2e4c3fb6a090.png)

3.5 mil gap near IC18. Is that ok? Did they fix that in the fab?

sbourdeauducq · 2018-01-03T08:06:08Z

@marmeladapk @gkasprow ping

gkasprow · 2018-01-03T08:50:59Z

@jordens in IC17, the DIR is H so it means A -> B direction which is correct
But on IC19 channel 1 direction is B->A which is wrong.
Channel 2 direction is A -> B which is also wrong. This explains why it does not work
You can simply short pins 8, 5 and 9,4, we will fix it the right way on remaining boards.

jordens · 2018-01-03T09:08:03Z

Yes, that's what I said.
Could you implement your fix and show me (photo) what you mean? Just shorting still has the same contention issue. You know better where to cut and scratch the lines.

hartytp · 2018-01-26T12:19:17Z

TR1 to TC2-1TX+ for my boards

Let's do this for all boards then. I want to minimize the number of population variants floating around for this hardware.

jordens · 2018-01-28T22:18:43Z

@marmeladapk I saw your note on the XADC issues. Are you using vivado with JTAG to access the XADC directly or do you have gateware that you are using to access it?

gkasprow · 2018-01-28T22:21:16Z

we use Vivado, I also observed such effect. But after some time it started working.

…

sbourdeauducq · 2018-01-29T04:16:42Z

I am not overly excited to see the I2C bus and the UART scattered over the banks on the FPGA. The various SFP control lines would have been better candidates for scattering. But I think this is OK for now (@sbourdeauducq could you confirm?)

I2C and UART are low-speed signals, and they are using the most regular FPGA IO (no clock-capable pins etc.). So there shouldn't be an issue with scattering them.

jordens · 2018-01-29T15:03:28Z

@marmeladapk "The XADC also has an on-chip reference option which is selected by connecting VREFP and VREFN to ADCGND": replace C49 with a 0R. (added to top post).

marmeladapk · 2018-01-30T02:38:37Z

@jordens I connected it without a jumper. C49 was in 0201 case, our jumpers are 0402, there's no way I could fit that under FPGA.

jordens · 2018-01-30T04:09:26Z

@marmeladapk thanks.

marmeladapk · 2018-01-30T15:10:23Z

@jordens If I just flip TC2-1TX+ by 180 deg. then output will be swapped (_P line with _N line). Do we care? I can connect CLK_IN to pin 4 if we want to avoid that.

(up - current balun, down, TC2-1TX+ rotaded 180 deg.)

jordens · 2018-01-30T15:22:56Z

@marmeladapk Correct (well observed!). The swapped polarity doesn't hurt me but if you want (and for the perfectionists inside us) swapping the connection on the primary (6-4) is nicer.

marmeladapk · 2018-01-30T17:59:34Z

I finished, but I'll upload documentation from my home computer, as here I've got some issues with generating it (new Altium... ).

marmeladapk · 2018-01-31T09:46:54Z

@jordens @hartytp I released rc3. Unless you have any objection I'd like to send it to the manufacturer.

jordens · 2018-01-31T09:56:36Z

@marmeladapk thanks! Give me an hour to check it.

hartytp · 2018-01-31T10:52:06Z

@marmeladapk looks beautiful. If I had to nit pick, I'd probably suggest adding a PN for that clock balun on the schematic. Otherwise, no comments here apart from send it off! Great work!

jordens · 2018-01-31T10:54:54Z

@marmeladapk Good to go! Send it!

hartytp · 2018-01-31T10:58:37Z

Whooo!

marmeladapk · 2018-01-31T11:03:11Z

@hartytp I'll fix schematics in the final version.

marmeladapk · 2018-01-31T11:39:05Z

Note to self: I unmasked thermal vias.

marmeladapk · 2018-02-02T21:39:37Z

As a part of one of my projects on uni I wrote code that controls all parameters of Si5324. It abstracts all the registers stuff, allows to set desired input clock and output frequency (but only on one output). It finds right divider values so you don't need to use DSPLLsim for this but it does so using brute force method. In all cases I tested it found right values in <0.5 second (even with odd frequencies like 192.3 MHz). Do you want me to upload it for later use?

gkasprow · 2018-02-02T21:44:07Z

@marmeladapk ask @jordens

jordens · 2018-02-03T07:55:01Z

Integrate it into the code I posted before.

marmeladapk · 2018-02-21T10:51:53Z

@jordens V1.1 arrived yesterday. Unfortunately pyftdi resets all other outputs when using I2C, so we have to fall back to bitbang. :/

jordens · 2018-02-21T11:04:44Z

@marmeladapk You mean it messes with the other channels? Yes. I have seen that too.
Or do you mean it resets the other pins on the second channel? That should and can be fixed in pyftdi as well.
In both cases, could you file a bug with pyftdi if there isn't one yet?

jordens · 2018-02-21T11:05:12Z

Anyway, bitbanging I2C is just fine.

marmeladapk · 2018-02-27T13:59:48Z

@jordens @hartytp Unless anyone has any objections to schematics, I'd like to publish v1.1 and upload board files.

hartytp · 2018-02-27T14:01:56Z

Go for it.

jordens · 2018-02-27T14:24:19Z

👍

marmeladapk · 2018-02-28T11:52:07Z

v1.1 is released, so I'll go ahead and close this.

marmeladapk added area:hardware area:kasli labels Nov 6, 2017

marmeladapk self-assigned this Nov 6, 2017

jordens changed the title ~~Kasli rev 1.0 errata~~ Kasli v1.0 errata Nov 6, 2017

jordens added this to the Kasli v1.1 milestone Nov 6, 2017

marmeladapk mentioned this issue Dec 15, 2017

Kasli tests & errata #442

Closed

gkasprow changed the title ~~Kasli v1.0 errata~~ Kasli v1.0 tests & errata Dec 15, 2017

marmeladapk closed this as completed Feb 28, 2018

marmeladapk mentioned this issue Nov 24, 2018

Kasli 1.2 WR support sinara-hw/Kasli#25

Closed

jordens mentioned this issue Apr 5, 2019

Ground VP_0, VN_0? sinara-hw/Sayma_RTM#76

Closed

Kasli v1.0 tests & errata #349

Kasli v1.0 tests & errata #349

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