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Non-pipelined, single cycle, implementation of MIPS (32 bits) processor

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CSE_Bubble

This repository contains the implementation of the problem statement.

The detailed explanation of the approach is documented in Report.

To run the code:

  1. go to the src directory
  2. complile CSE_Bubble_tb.v and run the executable

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Non-pipelined, single cycle, implementation of MIPS (32 bits) processor

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