Name		Name	Last commit message	Last commit date
Latest commit History 27 Commits
02_ddr_init/vivado		02_ddr_init/vivado
03_ddr_wr_ctrl/vivado		03_ddr_wr_ctrl/vivado
04_ddr_rd_ctrl		04_ddr_rd_ctrl
05_ddr_wr_rd_fifo/vivado		05_ddr_wr_rd_fifo/vivado
06_ddr_user_ctrl/vivado		06_ddr_user_ctrl/vivado
07_ddr_hdmi		07_ddr_hdmi
08_uart_ddr_hdmi		08_uart_ddr_hdmi
09_Gige_HDMI/vivado/Gige_HDMI		09_Gige_HDMI/vivado/Gige_HDMI
10_rx_filter_crc		10_rx_filter_crc
12_gen_heart_beat/vivado		12_gen_heart_beat/vivado
13_add_check_sum/vivado		13_add_check_sum/vivado
14_tx_crc_oddr		14_tx_crc_oddr
test01_ddr_init		test01_ddr_init
test02_ddr_wr_ctrl		test02_ddr_wr_ctrl
test03_ddr_rd_ctrl		test03_ddr_rd_ctrl
test04_ddr_wr_rd_fifo		test04_ddr_wr_rd_fifo
test05_ddr_user_ctrl		test05_ddr_user_ctrl
test06_ddr_hdmi		test06_ddr_hdmi
test07_uart_ddr_hdmi/doc		test07_uart_ddr_hdmi/doc
test08_Gige_RGMII		test08_Gige_RGMII
test09_rx_filter_crc		test09_rx_filter_crc
test11_gen_heart_beat		test11_gen_heart_beat
test12_add_check_sum		test12_add_check_sum
test13_tx_crc_oddr		test13_tx_crc_oddr
LICENSE		LICENSE
README.md		README.md

Repository files navigation

v3edu

test of v3edu FPGA train