Home

RISC-V is an open standard instruction set architecture based on established RISC principles.

A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available, and the instruction set is supported in several popular software toolchains.

Notable features of the RISC-V ISA include instruction bit field locations chosen to simplify the use of multiplexers in a CPU, : 17  a design that is architecturally neutral, and most-significant bits of immediate values placed at a fixed location to speed sign extension.

RISC is a computer architecture or modern computing architecture with the simplest instructions and execution types. This architecture is used in high-performance computers, such as vector computers. Besides being used in vector computers, this design is also implemented in other computer processors, such as in some Intel 960 microprocessors, Itanium (IA64) from Intel Corporation, Alpha AXP from DEC, R4x00 from MIPS Corporation, PowerPC and POWER architecture from International Business Machine. In addition, RISC is also commonly used in Advanced RISC Machine (ARM) and StrongARM (including Intel XScale), SPARC and UltraSPARC from Sun Microsystems, and PA-RISC from Hewlett-Packard.

Various applications for RISC-V include:

• Artificial intelligence
• Augmented reality
• Automotive
• Cloud servers
• Computer devices and controllers
• General purpose processors
• Internet of Things
• Machine learning
• Network edge
• Virtual reality

RISC-V Characteristics

Is a proven ISA and follows established RISC design principles Has single-cycle instructions Uses a load-store architecture Features a simple, stable, software-centric design (small, fixed base with modular fixed-standard extensions) Is modular, layered and extensible, allowing for software and hardware freedom on architecture Flexible and scalable (i.e., suitable for microcontrollers to personal computers to supercomputers) Has 32- and 64-bit variants and extensions to support floating point instructions Is supported by various language compilers (e.g., GNU Compiler Collection and Linux operating system) Offers a range of hardware support from microcontrollers to systems on module, systems on chip and field programmable gate arrays Accelerates the design-to-market timeline through collaboration and open source IP reuse

RISC-V software includes toolchains, operating systems, middleware[vague] and design software.

Available RISC-V software tools include a GNU Compiler Collection toolchain, an LLVM toolchain, the OVPsim simulator, the Spike simulator, and a simulator in QEMU. JEP 422: Linux/RISC-V Port is already integrated into mainline OpenJDK repository.

The preliminary FreeBSD port to the RISC-V architecture was upstreamed in February 2016, and shipped in FreeBSD 11.0.

UEFI Spec v2.7 has defined the RISC-V binding and a TianoCore port has been done by HPE engineers and is expected to be upstreamed.

Hex Five released the first Secure IoT Stack for RISC-V with FreeRTOS support.

Pharos RTOS has been ported to 64-bit RISC-V. Also see Comparison of real-time operating systems.

A simulator exists to run a RISC-V Linux system on a web browser using JavaScript.

QEMU supports running 32- and 64-bit RISC-V systems with a number of emulated or virtualized devices, as well as running RISC-V Linux binaries.

RISC is currently not as widely used as the ARM architecture, but The cost reduction and a large number of resource sharing brought about by its open source make it not affected by high licensing fees and development agreements. It still has a certain potential in the market and has brought great help to public education. RISC-V is really unique because it is a common, free, open-source ISA to which software can be ported, hardware can be developed, enables innovation and has a great community, can accelerate the development of open computing architectures specifically designed for the Big Data environment and processors can be built to support it.