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UNOFFICIAL bug tracker for the RISC-V specifications

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This is a dummy repository to track issues with the specification until the official RISC-V specs move to GitHub.

I'm inspired by https://github.com/rust-lang/rfcs and I'd like to move more in that direction. But I'm just one person, not a subteam, so not all the process will be implemented.

We could have a very rushed 2.0 and a 3.0 sometime before CY2020, but I'd rather we be a little more methodical about it. So this repository will focus on issues that need to be resolved or clearly roadmapped for an awesome 2.0, in particular the following scopes:

  • Strictly editorial issues

  • Features for which, what people will do if the feature is missing, is dramatically less compatible than the feature itself would be

  • Things that, if frozen in 2.0, are likely to be regarded as "baggage"

  • Things that take far too much of their fair share of the weirdness budget

  • Actual implementation problems, reported by people doing actual implementations

Features or changes which can be done compatibly later, especially those which require a large amount of discussion like transactional memory, are probably best suited for another forum. We'll see.

Please keep discussion focused on the specific issue for any given thread. Offtopic comments will be deleted.

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UNOFFICIAL bug tracker for the RISC-V specifications

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