Fix SPI #9
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Fix SPI #9
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−498
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added 5 commits
November 25, 2019 10:25
"Data is latched on the rising edge of SCLK" - this is CPHA = 0. It's not clear what CPOL is but mode 3 is not CPHA = 1 which causes SPI to not work on some platforms (Artemis).
IC can't communicate with SPI freqs above 7MHz. And some platforms (looking at you Artemis) will run the SPI clock at 7.125MHz when started at 7MHz breaking the first example.
A 4MHz default is more safe. More platforms have a good divisor at 4MHz rather than 6MHz or 7MHz so we are more likely not to violate the 7MHz max SPI speed.
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Main problem: SPI is mode0 not mode3. Also, Artemis @7MHz is actually 7.125MHz.
These changes make ICM examples in SPI mode correctly operate on Artemis. I tested the changes against Artemis and Uno and both work well. I can test other platforms as needed. Let me know what platform you did your SPI testing on.
Here is the pertinent datasheet section:
Here are the SPI modes:
Here is how Logic describes the modes:
To match datasheet, CPHA must be 0 (mode 0 or 2). It is not clear from the datasheet what CPOL needs to be but mode 3 (CPHA = 1) causes the Artemis to check the data on the falling edge of the clock which causes comm to fail.
Artemis running at 7.1xx MHz instead of 7MHz (causes comm to fail):