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@jakubcabal

Jakub Cabal

jakubcabal
Czech Republic

Hello everyone. πŸ‘‹

My name is Jakub Cabal and I am an FPGA engineer πŸ‘¨β€πŸ’» and creator of several open-source RTL projects including those listed below. In my work, I mainly focus on the processing of network traffic 🌐 on FPGAs and I also have experience with several communication interfaces, including Ethernet and PCIe.

  • rmii-firewall-fpga = The RMII Firewall FPGA allows to filter Ethernet packets.
  • spi-fpga = The SPI master and SPI slave are simple controllers FPGAs.
  • uart-for-fpga = The simple UART for FPGA is UART controller for serial communication.

Your support will help me further develop interesting open-source projects built on FPGA or create new useful open-source RTL IP cores. Your ideas πŸ’‘ are also welcome.

Thank you for your support! πŸ’™

Featured work

  1. jakubcabal/uart-for-fpga

    Simple UART controller for FPGA written in VHDL

    VHDL 90
  2. jakubcabal/spi-fpga

    SPI master and SPI slave for FPGA written in VHDL

    VHDL 164
  3. jakubcabal/pipemania-fpga-game

    Pipe Mania - Game for FPGA written in VHDL

    VHDL 9
  4. jakubcabal/sdram-tester-fpga

    SDRAM Tester implemented in FPGA

    VHDL 9
  5. jakubcabal/cyc1000-rsu

    The CYC1000 FPGA Remote System Upgrade project

    VHDL 7

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