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jakubcabal/README.md

Hi there 👋

I am FPGA engineer in Czech Republic, technology enthusiast, food lover and Linux user (Fedora).

  • 🏢 I'm currently working at CESNET z.s.p.o.
  • 🎓 My Alma mater: Brno University of Technology
  • 📫 How to reach me: Twitter, Telegram
  • Fun fact: I know my ancestors until the 17th century.

Popular repositories

  1. spi-fpga Public

    SPI master and SPI slave for FPGA written in VHDL

    VHDL 96 25

  2. Simple UART controller for FPGA written in VHDL

    VHDL 61 22

  3. Pipe Mania - Game for FPGA written in VHDL

    VHDL 8 1

  4. RMII Firewall FPGA

    VHDL 8 3

  5. SDRAM Tester implemented in FPGA

    VHDL 7 1

  6. The CYC1000 FPGA Remote System Upgrade project

    VHDL 5

135 contributions in the last year

Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul Mon Wed Fri

Contribution activity

August 2022

jakubcabal has no activity yet for this period.

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