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sumitarohit/README.md

"Hello there! I'm Rohit Kumar, a final-year student pursuing B.Tech in Electronics and Communication Engineering at Guru Jambheshwar University of Science and Technology, Hisar. With an insatiable curiosity and a passion for innovation, I thrive on learning new concepts and pushing the boundaries of technology.

My journey in the realm of electronics has been enriched by a two-month summer training in VLSI Design at NIELIT New Delhi, where I honed my skills in Verilog, VHDL, Digital Design,FPGA Prototyping and Mini Project (UART). My coursework in Digital Electronics, Analog Electronics and CMOS Fundamentals has further solidified my foundation in the field.

I find joy in connecting with people and engaging in meaningful conversations, and I'm always eager to share knowledge and exchange ideas. When I'm not immersed in the world of electronics, you'll likely find me enjoying a game of chess or exploring new paths on my bicycle.

Driven by a desire to explore and make a difference, I am currently seeking opportunities for an internship in frontend VLSI design. With experience in tools like Xilinx Vivado Design Suite, LTSpice, and P Spice, I am ready to contribute to innovative projects and continue my journey of growth and discovery in the exciting field of electronics and communication engineering."

Let's connect and explore the possibilities together!

Popular repositories Loading

  1. Array_Multiplier_project Array_Multiplier_project Public

    This is a 4*4 Array_Multiplier_project using Verilog HDL. This is successfully implemented on FPGA board.

    Tcl

  2. Seven_segment_display_hex Seven_segment_display_hex Public

    Verilog

  3. UART_Using_Verilog_HDl UART_Using_Verilog_HDl Public

    Verilog

  4. ARITHMETIC_LOGIC_UNIT ARITHMETIC_LOGIC_UNIT Public

    Tcl

  5. sumitarohit sumitarohit Public

    Config files for my GitHub profile.