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Improve memory read/write #122
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semu.c applies the technique Duff's device to generalize memory operations. See |
jserv
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Improve the performance of memory read and write
Improve memory read/write
Apr 6, 2023
This was referenced Apr 6, 2023
qwe661234
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Apr 10, 2023
After analyzing the data collected during the execution of the Dhrystone benchmark, we found that the primary performance bottleneck lies in memory read/write operations. To address this issue, we modified the implementation of memory read/write by eliminating unnecessary checks and replacing slow operations with more efficient ones. Additionally, we integrated a simple memory pool and resolved the issue of disabled misaligned memory access, the user can add argument `--misalign` to enable misaligned memory access. Based on performance results from running Dhrystone, we observed a significant improvement following our enhancements to the memory I/O. | Test | 66200d0 | improvement |Speedup| |------------+--------------+-----------------+-------| | Dhrystone | 815 DMIPS | 1245 DMIPS | +52.7%| Close sysprog21#122
qwe661234
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Apr 10, 2023
After analyzing the data collected during the execution of the Dhrystone benchmark, we found that the primary performance bottleneck lies in memory read/write operations. To address this issue, we modified the implementation of memory read/write by eliminating unnecessary checks and replacing slow operations with more efficient ones. Additionally, we integrated a simple memory pool and resolved the issue of disabled misaligned memory access, the user can add argument `--misalign` to enable misaligned memory access. Based on performance results from running Dhrystone, we observed a significant improvement following our enhancements to the memory I/O. | Test | 66200d0 | improvement |Speedup| |------------+--------------+-----------------+-------| | Dhrystone | 815 DMIPS | 1245 DMIPS | +52.7%| Close sysprog21#122
qwe661234
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Apr 10, 2023
After analyzing the data collected during the execution of the Dhrystone benchmark, it was discovered that the primary performance bottleneck lies in memory read/write operations. To address this issue, modifications were made to the implementation of memory read/write operations, eliminating unnecessary checks and replacing slow operations with more efficient ones. Additionally, a simple memory pool was integrated. It is now possible for the user to enable misaligned memory access by launching with option "--misalign". The enhancements made to the memory I/O resulted in a significant improvement, as observed through performance results obtained by running Dhrystone. | Test | 66200d0 | improvement |Speedup| |------------+--------------+-----------------+-------| | Dhrystone | 815 DMIPS | 1245 DMIPS | +52.7%| Close sysprog21#122
qwe661234
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Apr 11, 2023
After analyzing the data collected during the execution of the Dhrystone benchmark, it was discovered that the primary performance bottleneck lies in memory read/write operations. To address this issue, modifications were made to the implementation of memory read/write operations, eliminating unnecessary checks and replacing slow operations with more efficient ones. Additionally, a simple memory pool was integrated. It is now possible for the user to enable misaligned memory access by launching with option "--misalign". The enhancements made to the memory I/O resulted in a significant improvement, as observed through performance results obtained by running Dhrystone. | Test | 66200d0 | improvement |Speedup| |------------+--------------+-----------------+-------| | Dhrystone | 815 DMIPS | 1245 DMIPS | +52.7%| Close sysprog21#122
2011eric
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Jul 22, 2023
After analyzing the data collected during the execution of the Dhrystone benchmark, it was discovered that the primary performance bottleneck lies in memory read/write operations. To address this issue, modifications were made to the implementation of memory read/write operations, eliminating unnecessary checks and replacing slow operations with more efficient ones. Additionally, a simple memory pool was integrated. It is now possible for the user to enable misaligned memory access by launching with option "--misalign". The enhancements made to the memory I/O resulted in a significant improvement, as observed through performance results obtained by running Dhrystone. | Test | 66200d0 | improvement |Speedup| |------------+--------------+-----------------+-------| | Dhrystone | 815 DMIPS | 1245 DMIPS | +52.7%| Close sysprog21#122
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After analyzing the data collected during the execution of the dhrystone benchmark, it becomes evident that the primary performance bottleneck lies in memory read and write operations. To address this issue and improve performance, we should consider modifying the implementation of these memory operations.
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