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Improve memory read/write #122

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qwe661234 opened this issue Apr 5, 2023 · 1 comment
Closed

Improve memory read/write #122

qwe661234 opened this issue Apr 5, 2023 · 1 comment

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@qwe661234
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After analyzing the data collected during the execution of the dhrystone benchmark, it becomes evident that the primary performance bottleneck lies in memory read and write operations. To address this issue and improve performance, we should consider modifying the implementation of these memory operations.

  21.15%  rv32emu  rv32emu           [.] memory_write
  17.21%  rv32emu  rv32emu           [.] do_sw
  12.82%  rv32emu  rv32emu           [.] do_lw
   6.89%  rv32emu  rv32emu           [.] memory_read_w
   6.68%  rv32emu  rv32emu           [.] on_mem_write_w

@jserv
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jserv commented Apr 5, 2023

semu.c applies the technique Duff's device to generalize memory operations. See ram_load and ram_store.
We may eliminate unnecessary range checks for memory chunks. Furthermore, memory chunk in src/io.c is not really vital for implementing RV32 emulation though.

@jserv jserv changed the title Improve the performance of memory read and write Improve memory read/write Apr 6, 2023
qwe661234 added a commit to qwe661234/rv32emu that referenced this issue Apr 10, 2023
After analyzing the data collected during the execution of the Dhrystone
benchmark, we found that the primary performance bottleneck lies in memory
read/write operations. To address this issue, we modified the implementation
of memory read/write by eliminating unnecessary checks and replacing slow
operations with more efficient ones. Additionally, we integrated a simple
memory pool and resolved the issue of disabled misaligned memory access,
the user can add argument `--misalign` to enable misaligned memory access.

Based on performance results from running Dhrystone, we observed a significant
improvement following our enhancements to the memory I/O.

|    Test    |    66200d0   |   improvement   |Speedup|
|------------+--------------+-----------------+-------|
| Dhrystone  | 815 DMIPS    |   1245 DMIPS    | +52.7%|

Close sysprog21#122
qwe661234 added a commit to qwe661234/rv32emu that referenced this issue Apr 10, 2023
After analyzing the data collected during the execution of the Dhrystone
benchmark, we found that the primary performance bottleneck lies in memory
read/write operations. To address this issue, we modified the implementation
of memory read/write by eliminating unnecessary checks and replacing slow
operations with more efficient ones. Additionally, we integrated a simple
memory pool and resolved the issue of disabled misaligned memory access,
the user can add argument `--misalign` to enable misaligned memory access.

Based on performance results from running Dhrystone, we observed a significant
improvement following our enhancements to the memory I/O.

|    Test    |    66200d0   |   improvement   |Speedup|
|------------+--------------+-----------------+-------|
| Dhrystone  | 815 DMIPS    |   1245 DMIPS    | +52.7%|

Close sysprog21#122
qwe661234 added a commit to qwe661234/rv32emu that referenced this issue Apr 10, 2023
After analyzing the data collected during the execution of the Dhrystone
benchmark, it was discovered that the primary performance bottleneck lies
in memory read/write operations. To address this issue, modifications were
made to the implementation of memory read/write operations, eliminating
unnecessary checks and replacing slow operations with more efficient ones.
Additionally, a simple memory pool was integrated. It is now possible for
the user to enable misaligned memory access by launching with option "--misalign".

The enhancements made to the memory I/O resulted in a significant improvement,
as observed through performance results obtained by running Dhrystone.

|    Test    |    66200d0   |   improvement   |Speedup|
|------------+--------------+-----------------+-------|
| Dhrystone  | 815 DMIPS    |   1245 DMIPS    | +52.7%|

Close sysprog21#122
qwe661234 added a commit to qwe661234/rv32emu that referenced this issue Apr 11, 2023
After analyzing the data collected during the execution of the Dhrystone
benchmark, it was discovered that the primary performance bottleneck lies
in memory read/write operations. To address this issue, modifications were
made to the implementation of memory read/write operations, eliminating
unnecessary checks and replacing slow operations with more efficient ones.
Additionally, a simple memory pool was integrated. It is now possible for
the user to enable misaligned memory access by launching with option "--misalign".

The enhancements made to the memory I/O resulted in a significant improvement,
as observed through performance results obtained by running Dhrystone.

|    Test    |    66200d0   |   improvement   |Speedup|
|------------+--------------+-----------------+-------|
| Dhrystone  | 815 DMIPS    |   1245 DMIPS    | +52.7%|

Close sysprog21#122
@jserv jserv closed this as completed in 78112c3 Apr 11, 2023
2011eric pushed a commit to 2011eric/rv32emu that referenced this issue Jul 22, 2023
After analyzing the data collected during the execution of the Dhrystone
benchmark, it was discovered that the primary performance bottleneck lies
in memory read/write operations. To address this issue, modifications were
made to the implementation of memory read/write operations, eliminating
unnecessary checks and replacing slow operations with more efficient ones.
Additionally, a simple memory pool was integrated. It is now possible for
the user to enable misaligned memory access by launching with option "--misalign".

The enhancements made to the memory I/O resulted in a significant improvement,
as observed through performance results obtained by running Dhrystone.

|    Test    |    66200d0   |   improvement   |Speedup|
|------------+--------------+-----------------+-------|
| Dhrystone  | 815 DMIPS    |   1245 DMIPS    | +52.7%|

Close sysprog21#122
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