Introduce baseline JIT compiler #135

qwe661234 · 2023-06-01T09:46:36Z

The baseline JIT compiler design involves tracing an EBB when its usage frequency exceeds a predetermined threshold. We then utilize a code generator to convert the instruction sequence into C code. The C code is subsequently compiled using mir, and the resulting target machine code is stored in the code cache for future utilization.

The primary objective of introducing the baseline JIT compiler is to enhance the execution speed of RISC-V instructions with minimal modification. This implementation requires three additional components: a code generator, mir compiler, and code cache, while maintaining the original design of the interpreter. Furthermore, this baseline JIT compiler serves as the foundational target for future improvements.

Metric	master	baseline JIT	Speedup
CoreMark	1352.843 (Iterations/Sec)	1740.881 (Iterations/Sec)	+28.6％
dhrystone	1146 DMIPS	2368.33DMIPS	+106%

src/codegen.c

src/compile.c

src/cache.c

jserv

Resolve the issues raised by CodeQL in advance.

src/cache.c

src/codegen.c

solve sysprog21#135

Makefile

jserv · 2023-06-02T12:02:38Z

src/riscv_private.h

    block_map_t block_map; /**< basic block map */
+#else
+    struct cache *cache;


To minimize the code changes, is it possible to stick to block_map_t rather than struct cache?

It is difficult to stick to block_map_t, because the structure of ARC cache is totally different from block_map_t.

.vscode/settings.json

Makefile

src/codegen.c

src/elfdef.h

jserv · 2023-06-03T15:18:23Z

The proposed changes aim to achieve the following objectives:

Elimination of code duplication between emulate.c and codegen.c.
Reuse of the RV32 interpreter implementation for the baseline JIT.

These refinements focus on improving code organization and minimizing duplication. By reusing the existing RV32 interpreter implementation, we can expedite the development of the JIT compiler while maintaining consistency between the interpreter and JIT modes of execution.

The new branch wip/jit lays the groundwork for the future development of a baseline JIT compiler. By decoupling the RV32 instructions, we create reusable implementation templates that can be leveraged for code generation in the JIT compiler. This decoupling enables straightforward and flexible code generation strategies, eliminating the need for code duplication between the interpreter and MIR-based JIT compiler.

Assuming the existence of a dedicated shell script capable of generating C-string operations for each RVOP entry in src/codegen.c from src/rv32_template.c, the following procedure can be followed:

Enable the JIT compiler in the top-level configurations.
Generate src/codegen.c from src/rv32_template.c using the aforementioned script.
The file src/emulate.c includes the generated src/codegen.c for the JIT execution path.
The runtime determines the execution path, whether through the interpreter or JIT compilation, based on heuristic algorithms or thresholds.

This pull request should be on top of branch wip/jit, and you will have to rebase it and rework.

src/cache.c

jserv

Rebase latest wip/jit branch rather than master branch.

src/compile.c

tools/gen-jit-template.py

src/compile.c

Makefile

src/compile.c

src/cache.c

src/riscv.c

src/compile.c

jserv · 2023-06-12T00:26:28Z

It fails to build on macOS:

$ make  
Makefile:19: *** missing separator.  Stop.

System information:

$ make --version | head -1
GNU Make 3.81

src/compile.c

src/riscv_private.h

src/compile.c

The baseline JIT compiler design involves tracing an EBB when its usage frequency exceeds a predetermined threshold. We then utilize a code generator to convert the instruction sequence into C code. The C code is subsequently compiled using mir, and the resulting target machine code is stored in the code cache for future utilization. The primary objective of introducing the baseline JIT compiler is to enhance the execution speed of RISC-V instructions with minimal modification. This implementation requires three additional components: a code generator, mir compiler, and code cache, while maintaining the original design of the interpreter. Furthermore, this baseline JIT compiler serves as the foundational target for future improvements. | Metric | master | baseline JIT |Speedup | |-----------+-------------------------+--------------------------+--------| | CoreMark |1352.843 (Iterations/Sec)|1740.881 (Iterations/Sec) | +28.6% | | dhrystone |1146 DMIPS |2368.33 DMIPS | +106% |

qwe661234 · 2023-06-14T06:50:01Z

It fails to build on macOS:
$ make  
Makefile:19: *** missing separator.  Stop.
System information:
$ make --version | head -1
GNU Make 3.81

Solved

jserv · 2023-06-14T09:07:39Z

Runtime failure on macOS/Arm64. Reproduce:

$ git clone https://github.com/sysprog21/rv32emu
$ cd rv32emu
$ gh pr checkout 135
$ make ENABLE_JIT=1
$ make check

Error messages:

Assertion failed: (cache->jitcode != MAP_FAILED), function cache_create, file cache.c, line 316.
Assertion failed: (cache->jitcode != MAP_FAILED), function cache_create, file cache.c, line 316.
Assertion failed: (cache->jitcode != MAP_FAILED), function cache_create, file cache.c, line 316.
Running hello.elf ... Failed.

jserv · 2023-06-15T02:08:04Z

This preliminary work was integrated into wip/jit branch for sake of synchronization with latest master branch.
@qwe661234, You shall work on wip/jit branch for all JIT specific issues and submit pull requests on top of it.

The baseline JIT compiler design involves tracing an EBB when its usage frequency exceeds a predetermined threshold. We then utilize a code generator to convert the instruction sequence into C code. The C code is subsequently compiled using MIR, and the resulting target machine code is stored in the code cache for future utilization. The primary objective of introducing the baseline JIT compiler is to enhance the execution speed of RISC-V instructions with minimal modification. This implementation requires three additional components: a code generator, MIR compiler, and code cache, while maintaining the original design of the interpreter. Furthermore, this baseline JIT compiler serves as the foundational target for future improvements. | Metric | master | baseline JIT |Speedup | |-----------+-------------------------+--------------------------+--------| | CoreMark |1352.843 (Iterations/Sec)|1740.881 (Iterations/Sec) | +28.6% | | dhrystone |1146 DMIPS |2368.33 DMIPS | +106% | Known issue: this implementation does not work on Arm64 architecture.

The baseline JIT compiler design involves tracing an EBB when its usage frequency exceeds a predetermined threshold. We then utilize a code generator to convert the instruction sequence into C code. The C code is subsequently compiled using MIR, and the resulting target machine code is stored in the code cache for future utilization. The primary objective of introducing the baseline JIT compiler is to enhance the execution speed of RISC-V instructions with minimal modification. This implementation requires three additional components: a code generator, MIR compiler, and code cache, while maintaining the original design of the interpreter. Furthermore, this baseline JIT compiler serves as the foundational target for future improvements. | Metric | master | baseline JIT |Speedup | |-----------+-------------------------+--------------------------+--------| | CoreMark |1352.843 (Iterations/Sec)|1740.881 (Iterations/Sec) | +28.6% | | dhrystone |1146 DMIPS |2368.33 DMIPS | +106% | Known issue: this implementation does not correctly work on Apple M1 MacOS.

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qwe661234 force-pushed the baseline_JIT branch from 5cfd6b8 to 0f13900 Compare June 2, 2023 09:09

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Fix spicious pointer scaling

b0f7b65

solve sysprog21#135

qwe661234 mentioned this pull request Jun 2, 2023

Fix spicious pointer scaling #138

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