Removed parts of fixed/float package that confuses GHDL

talonmyburgh · May 25, 2023 · a9c15ff · a9c15ff
1 parent b214ab5
commit a9c15ff
Show file tree

Hide file tree

Showing 2 changed files with 1 addition and 161 deletions.
diff --git a/common_pkg/fixed_pkg_c.vhd b/common_pkg/fixed_pkg_c.vhd
@@ -1412,43 +1412,7 @@ package fixed_pkg is
 -- rtl_synthesis on
 -- pragma synthesis_on
 
-  -- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-  -- extra functions are needed for compatability.
-  function to_ufixed (
-    arg                  : STD_LOGIC_VECTOR;  -- shifted vector
-    constant left_index  : INTEGER;
-    constant right_index : INTEGER)
-    return UNRESOLVED_ufixed;
-
-  function to_ufixed (
-    arg      : STD_LOGIC_VECTOR;       -- shifted vector
-    size_res : UNRESOLVED_ufixed)       -- for size only
-    return UNRESOLVED_ufixed;
-
-  function to_sfixed (
-    arg                  : STD_LOGIC_VECTOR;  -- shifted vector
-    constant left_index  : INTEGER;
-    constant right_index : INTEGER)
-    return UNRESOLVED_sfixed;
 
-  function to_sfixed (
-    arg      : STD_LOGIC_VECTOR;       -- shifted vector
-    size_res : UNRESOLVED_sfixed)       -- for size only
-    return UNRESOLVED_sfixed;
-
-  -- unsigned fixed point
-  function to_UFix (
-    arg      : STD_LOGIC_VECTOR;
-    width    : NATURAL;                 -- width of vector
-    fraction : NATURAL)                 -- width of fraction
-    return UNRESOLVED_ufixed;
-
-  -- signed fixed point
-  function to_SFix (
-    arg      : STD_LOGIC_VECTOR;
-    width    : NATURAL;                 -- width of vector
-    fraction : NATURAL)                 -- width of fraction
-    return UNRESOLVED_sfixed;
 
 end package fixed_pkg;
 -------------------------------------------------------------------------------
@@ -8288,76 +8252,5 @@ package body fixed_pkg is
   end function from_hstring;
 -- pragma synthesis_on
 -- rtl_synthesis on
-  -- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-  -- extra functions are needed for compatability.
-  function to_ufixed (
-    arg                  : STD_LOGIC_VECTOR;  -- shifted vector
-    constant left_index  : INTEGER;
-    constant right_index : INTEGER)
-    return UNRESOLVED_ufixed is
-  begin
-    return to_ufixed (
-      arg => to_stdulogicvector (arg),
-      left_index => left_index,
-      right_index => right_index);
-  end function to_ufixed;
-
-  function to_ufixed (
-    arg      : STD_LOGIC_VECTOR;       -- shifted vector
-    size_res : UNRESOLVED_ufixed)       -- for size only
-    return UNRESOLVED_ufixed is
-  begin
-    return to_ufixed (
-      arg => to_stdulogicvector (arg),
-      size_res => size_res);
-  end function to_ufixed;
-
-  function to_sfixed (
-    arg                  : STD_LOGIC_VECTOR;  -- shifted vector
-    constant left_index  : INTEGER;
-    constant right_index : INTEGER)
-    return UNRESOLVED_sfixed is
-  begin
-    return to_sfixed (
-      arg => to_stdulogicvector (arg),
-      left_index => left_index,
-      right_index => right_index);
-  end function to_sfixed;
-
-  function to_sfixed (
-    arg      : STD_LOGIC_VECTOR;       -- shifted vector
-    size_res : UNRESOLVED_sfixed)       -- for size only
-    return UNRESOLVED_sfixed is
-  begin
-    return to_sfixed (
-      arg => to_stdulogicvector (arg),
-      size_res => size_res);
-  end function to_sfixed;
-
-  -- unsigned fixed point
-  function to_UFix (
-    arg      : STD_LOGIC_VECTOR;
-    width    : NATURAL;                 -- width of vector
-    fraction : NATURAL)                 -- width of fraction
-    return UNRESOLVED_ufixed is
-  begin
-    return to_UFix (
-      arg => to_stdulogicvector (arg),
-      width => width,
-      fraction => fraction);
-  end function to_UFix;
-
-  -- signed fixed point
-  function to_SFix (
-    arg      : STD_LOGIC_VECTOR;
-    width    : NATURAL;                 -- width of vector
-    fraction : NATURAL)                 -- width of fraction
-    return UNRESOLVED_sfixed is
-  begin
-    return to_SFix (
-      arg => to_stdulogicvector (arg),
-      width => width,
-      fraction => fraction);
-  end function to_SFix;
 
 end package body fixed_pkg;
diff --git a/common_pkg/float_pkg_c.vhd b/common_pkg/float_pkg_c.vhd
@@ -975,20 +975,9 @@ package float_pkg is
 -- pragma synthesis_on
   -- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
   -- extra functions are needed for compatability.
-  function to_float (
-    arg                     : STD_LOGIC_VECTOR;
-    constant exponent_width : NATURAL := float_exponent_width;  -- length of FP output exponent
-    constant fraction_width : NATURAL := float_fraction_width)  -- length of FP output fraction
-    return UNRESOLVED_float;
 
-  function to_float (
-    arg      : STD_LOGIC_VECTOR;
-    size_res : UNRESOLVED_float)
-    return UNRESOLVED_float;
 
-  -- For Verilog compatability
-  function realtobits (arg : REAL) return STD_LOGIC_VECTOR;
-  function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL;
+
 
 end package float_pkg;
 -------------------------------------------------------------------------------
@@ -1079,11 +1068,6 @@ package body float_pkg is
     return or_reduce (STD_ULOGIC_VECTOR (arg));
   end function or_reduce;
 
-  function or_reduce (arg : STD_LOGIC_VECTOR)
-    return STD_ULOGIC is
-  begin
-    return or_reduce (STD_ULOGIC_VECTOR (arg));
-  end function or_reduce;
 
   -- purpose: AND all of the bits in a vector together
   -- This is a copy of the proposed "and_reduce" from 1076.3
@@ -7083,45 +7067,8 @@ package body float_pkg is
   end function from_hstring;
 -- rtl_synthesis on
 -- pragma synthesis_on
-  function to_float (
-    arg                     : STD_LOGIC_VECTOR;
-    constant exponent_width : NATURAL := float_exponent_width;  -- length of FP output exponent
-    constant fraction_width : NATURAL := float_fraction_width)  -- length of FP output fraction
-    return UNRESOLVED_float is
-  begin
-    return to_float (
-      arg            => to_stdulogicvector (arg),
-      exponent_width => exponent_width,
-      fraction_width => fraction_width);
-  end function to_float;
 
-  function to_float (
-    arg      : STD_LOGIC_VECTOR;
-    size_res : UNRESOLVED_float)
-    return UNRESOLVED_float is
-  begin
-    return to_float (
-      arg      => to_stdulogicvector (arg),
-      size_res => size_res);
-  end function to_float;
 
-  -- For Verilog compatability
-  function realtobits (arg : REAL) return STD_LOGIC_VECTOR is
-    variable result : float64;          -- 64 bit floating point
-  begin
-    result := to_float (arg => arg,
-                        exponent_width => float64'high,
-                        fraction_width => -float64'low);
-    return to_slv (result);
-  end function realtobits;
 
-  function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL is
-    variable arg64 : float64;           -- arg converted to float
-  begin
-    arg64 := to_float (arg => arg,
-                       exponent_width => float64'high,
-                       fraction_width => -float64'low);
-    return to_real (arg64);
-  end function bitstoreal;
 
 end package body float_pkg;