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Fix SPI blocking problem #1
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PB2 does not have any SPI1 alternate functions. However, PB3 has SPI1_SCK as it's alternate function 0. This uses PB3 correctly. Fixes 98227f2 ("Added SPI code and an APA102C example") Signed-off-by: Austin Glaser <austin.glaser@gmail.com>
The SPI peripheral on the STM32F0x2 has a configurable FIFO threshold (it can be either 8 or 16 bit, with the FIFO capacity being 32 bits). This threshold is controlled by the `FRXTH` bit in the `CR2` register (reference manual, pp 804). When using the default blocking implementation, the driver will write and the read bytes alternately. When the FIFO threshold is too high, the `RXNE` bit is not set after the first word -- and the driver blocks indefinitely. The presence of the FIFO suggests the possibility of a more efficient, non-default blocking implementation, which uses the FIFO to help pack transfers together more tightly and hence achieve a higher throughput. Fixes 98227f2 ("Added SPI code and an APA102C example") Signed-off-by: Austin Glaser <austin.glaser@gmail.com>
therealprof
approved these changes
Mar 21, 2018
I should hope so! I've got some more improvements to this particular driver I'm contemplating, including a non-default blocking implementation. Would you be open to merging another pull request some time in the next couple weeks? |
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Absolutely, keep 'em coming! |
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The SPI peripheral's receive FIFO threshold was too high -- it expected two bytes, but only one was transferred before blocking. I've fixed that issue.
Going forward,
stm32f30x-halis a better reference than thef103for the SPI peripheral on thef0x2devices.See the commit messages for more detailed explanations.