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VHDL implementation of a systolic array for computing SHA-256 for Bitcoin
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src Initial commit. Fully functional. Apr 28, 2013
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Hashpipe is a SHA-256 hardware hashing engine implemented in VHDL. It is designed as a systolic array, producing one hash per clock cycle.


The core has been synthesized and simulated in Quartus II on an Altera Cyclone III 120K FPGA. Two instances fit on this device, with an Fmax of approximately 70 MHz, thus producing together 140 MHash/sec.

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