mpfs_opensbi: Re-organize SBI areas so that RW areas follow each other

.github/workflows/build.yml

@@ -67,13 +67,13 @@ jobs:
             # Determine the repo and leave that unset to use the normal checkout behavior
             # of using the merge commit instead of HEAD
             case $GITHUB_REPOSITORY in
-              "apache/nuttx")
+              "tiiuae/nuttx")
                 # OS
                 echo "Triggered by change in OS"
                 APPS_REF=$REF_NAME
                 ;;
 
-              "apache/nuttx-apps" )
+              "tiiuae/incubator-nuttx-apps" )
                 # APPS
                 OS_REF=$REF_NAME
                 echo "Triggered by change in APPS"
@@ -91,7 +91,7 @@ jobs:
       - name: Checkout nuttx repo
         uses: actions/checkout@v3
         with:
-          repository: apache/nuttx
+          repository: tiiuae/nuttx
           ref: ${{ steps.gittargets.outputs.os_ref }}
           path: sources/nuttx
           fetch-depth: 1
@@ -101,7 +101,7 @@ jobs:
       - name: Checkout apps repo
         uses: actions/checkout@v3
         with:
-          repository: apache/nuttx-apps
+          repository: tiiuae/incubator-nuttx-apps
           ref: ${{ steps.gittargets.outputs.apps_ref }}
           path: sources/apps
           fetch-depth: 1
@@ -123,7 +123,7 @@ jobs:
 
     strategy:
       matrix:
-        boards: [arm-01, arm-02, arm-03, arm-04, arm-05, arm-06, arm-07, arm-08, arm-09, arm-10, arm-11, arm-12, arm-13, other, risc-v, sim-01, sim-02, xtensa, codechecker]
+        boards: [arm-12, risc-v]
 
     steps:
       - name: Download Source Artifact
@@ -173,6 +173,7 @@ jobs:
         continue-on-error: true
 
   macOS:
+    if: ${{ false }}  # disable for now
     permissions:
       contents: none
     runs-on: macos-13

.github/workflows/check.yml

@@ -32,7 +32,7 @@ jobs:
       - name: Checkout nuttx repo
         uses: actions/checkout@v3
         with:
-          repository: apache/nuttx
+          repository: tiiuae/nuttx
           path: nuttx
           fetch-depth: 0
 

arch/arm/src/stm32f7/stm32_ethernet.c

@@ -3136,7 +3136,9 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv)
 
 static int stm32_phyinit(struct stm32_ethmac_s *priv)
 {
+#ifdef CONFIG_STM32F7_AUTONEG
   volatile uint32_t timeout;
+#endif
   uint32_t regval;
   uint16_t phyval;
   int ret;

arch/risc-v/Kconfig

@@ -149,7 +149,6 @@ config ARCH_CHIP_MPFS
 	select ARCH_HAVE_SPI_CS_CONTROL
 	select ARCH_HAVE_PWM_MULTICHAN
 	select ARCH_HAVE_S_MODE
-	select PMP_HAS_LIMITED_FEATURES
 	select ONESHOT
 	select ALARM_ARCH
 	---help---
@@ -321,29 +320,6 @@ config ARCH_USE_S_MODE
 		and/or U-mode (in case of separate kernel-/userspaces). This provides
 		an option to run the kernel in S-mode, if the target supports it.
 
-# MPU has certain architecture dependent configurations, which are presented
-# here. Default is that the full RISC-V PMP specification is supported.
-
-config PMP_HAS_LIMITED_FEATURES
-	bool
-	default n
-
-config ARCH_MPU_MIN_BLOCK_SIZE
-	int "Minimum MPU (PMP) block size"
-	default 4	if !PMP_HAS_LIMITED_FEATURES
-
-config ARCH_MPU_HAS_TOR
-	bool "PMP supports TOR"
-	default y	if !PMP_HAS_LIMITED_FEATURES
-
-config ARCH_MPU_HAS_NO4
-	bool "PMP supports NO4"
-	default y	if !PMP_HAS_LIMITED_FEATURES
-
-config ARCH_MPU_HAS_NAPOT
-	bool "PMP supports NAPOT"
-	default y	if !PMP_HAS_LIMITED_FEATURES
-
 choice
 	prompt "Toolchain Selection"
 	default RISCV_TOOLCHAIN_GNU_RV64

arch/risc-v/src/common/Toolchain.defs

@@ -133,12 +133,17 @@ endif
 
 ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
 
-  # Generic GNU RVG toolchain
+  # Generic GNU RVG toolchain, prefer to use riscv-none-elf-gcc from xPack
+  # if CROSSDEV is not defined.
 
-  ifeq ($(CONFIG_RISCV_TOOLCHAIN_GNU_RV32),y)
-    CROSSDEV ?= riscv32-unknown-elf-
+  ifeq ($(shell riscv-none-elf-gcc --version > /dev/null 2>&1; echo $$?), 0)
+    CROSSDEV ?= riscv-none-elf-
   else
-    CROSSDEV ?= riscv64-unknown-elf-
+    ifeq ($(CONFIG_RISCV_TOOLCHAIN_GNU_RV32),y)
+      CROSSDEV ?= riscv32-unknown-elf-
+    else
+      CROSSDEV ?= riscv64-unknown-elf-
+    endif
   endif
 
   # Detect cpu ISA support flags
@@ -178,12 +183,14 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
     ARCHTYPE = rv64
     ARCHABITYPE = lp64
     LLVM_ARCHTYPE := riscv64
+    # https://www.sifive.com/blog/all-aboard-part-4-risc-v-code-models
+    ARCHCPUFLAGS = -mcmodel=medany
   endif
 
   # Construct arch flags
 
   ARCHCPUEXTFLAGS = i$(ARCHRVISAM)$(ARCHRVISAA)$(ARCHRVISAF)$(ARCHRVISAD)$(ARCHRVISAC)$(ARCHRVISAZ)
-  ARCHCPUFLAGS = -march=$(ARCHTYPE)$(ARCHCPUEXTFLAGS)
+  ARCHCPUFLAGS += -march=$(ARCHTYPE)$(ARCHCPUEXTFLAGS)
 
   # Construct arch abi flags
 

arch/risc-v/src/common/addrenv.h

@@ -58,7 +58,7 @@
 
 /* User address environment end */
 
-#define ARCH_ADDRENV_VEND       (ARCH_ADDRENV_VBASE + ARCH_ADDRENV_MAX_SIZE)
+#define ARCH_ADDRENV_VEND       (ARCH_ADDRENV_VBASE + ARCH_ADDRENV_MAX_SIZE - 1)
 
 /****************************************************************************
  * Public Function Prototypes

arch/risc-v/src/common/pgalloc.h

@@ -75,6 +75,10 @@ static inline uintptr_t riscv_pgvaddr(uintptr_t paddr)
     {
       return paddr - CONFIG_ARCH_PGPOOL_PBASE + CONFIG_ARCH_PGPOOL_VBASE;
     }
+  else if (paddr >= CONFIG_RAM_START && paddr < CONFIG_RAM_END)
+    {
+      return paddr - CONFIG_RAM_START + CONFIG_RAM_VSTART;
+    }
 
   return 0;
 }
@@ -95,7 +99,11 @@ static inline bool riscv_uservaddr(uintptr_t vaddr)
    * heap, or stack regions.
    */
 
-  return vaddr >= ARCH_ADDRENV_VBASE && vaddr < ARCH_ADDRENV_VEND;
+  return ((vaddr >= ARCH_ADDRENV_VBASE && vaddr < ARCH_ADDRENV_VEND)
+#ifdef CONFIG_ARCH_VMA_MAPPING
+       || (vaddr >= CONFIG_ARCH_SHM_VBASE && vaddr < ARCH_SHM_VEND)
+#endif
+      );
 }
 
 /****************************************************************************

arch/risc-v/src/common/riscv_addrenv.c

@@ -65,6 +65,7 @@
 #include <nuttx/compiler.h>
 #include <nuttx/irq.h>
 #include <nuttx/pgalloc.h>
+#include <nuttx/tls.h>
 
 #include <arch/barriers.h>
 
@@ -421,6 +422,12 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
 
   heapsize = heapsize + MM_PGALIGNUP(CONFIG_DEFAULT_TASK_STACKSIZE);
 
+#ifdef CONFIG_TLS_ALIGNED
+  /* Need more stack for TLS alignment */
+
+  heapsize += MM_PGALIGNUP(2 * TLS_MAXSTACK);
+#endif
+
   /* Map the reserved area */
 
   ret = create_region(addrenv, resvbase, resvsize, MMU_UDATA_FLAGS);
@@ -535,28 +542,24 @@ int up_addrenv_destroy(arch_addrenv_t *addrenv)
     {
       for (i = 0; i < ENTRIES_PER_PGT; i++, vaddr += pgsize)
         {
-          if (vaddr_is_shm(vaddr))
-            {
-              /* Do not free memory from SHM area */
-
-              continue;
-            }
-
           ptlast = (uintptr_t *)riscv_pgvaddr(mmu_pte_to_paddr(ptprev[i]));
           if (ptlast)
             {
-              /* Page table allocated, free any allocated memory */
-
-              for (j = 0; j < ENTRIES_PER_PGT; j++)
+              if (!vaddr_is_shm(vaddr))
                 {
-                  paddr = mmu_pte_to_paddr(ptlast[j]);
-                  if (paddr)
+                  /* Free the allocated pages, but not from SHM area */
+
+                  for (j = 0; j < ENTRIES_PER_PGT; j++)
                     {
-                      mm_pgfree(paddr, 1);
+                      paddr = mmu_pte_to_paddr(ptlast[j]);
+                      if (paddr)
+                        {
+                          mm_pgfree(paddr, 1);
+                        }
                     }
                 }
 
-              /* Then free the page table itself */
+              /* Regardless, free the page table itself */
 
               mm_pgfree((uintptr_t)ptlast, 1);
             }

arch/risc-v/src/common/riscv_addrenv_pgmap.c

@@ -202,7 +202,7 @@ int up_addrenv_kmap_pages(void **pages, unsigned int npages, uintptr_t vaddr,
 }
 
 /****************************************************************************
- * Name: riscv_unmap_pages
+ * Name: up_addrenv_kunmap_pages
  *
  * Description:
  *   Unmap a previously mapped virtual memory region.

arch/risc-v/src/common/riscv_addrenv_utils.c

@@ -63,24 +63,44 @@ uintptr_t riscv_get_pgtable(arch_addrenv_t *addrenv, uintptr_t vaddr)
   uintptr_t paddr;
   uintptr_t ptprev;
   uint32_t  ptlevel;
+  uint32_t  flags;
 
   /* Get the current level MAX_LEVELS-1 entry corresponding to this vaddr */
 
   ptlevel = ARCH_SPGTS;
   ptprev  = riscv_pgvaddr(addrenv->spgtables[ARCH_SPGTS - 1]);
-  paddr   = mmu_pte_to_paddr(mmu_ln_getentry(ptlevel, ptprev, vaddr));
+  if (!ptprev)
+    {
+      /* Something is very wrong */
+
+      return 0;
+    }
+
+  /* Find the physical address of the final level page table */
 
+  paddr = mmu_pte_to_paddr(mmu_ln_getentry(ptlevel, ptprev, vaddr));
   if (!paddr)
     {
       /* No page table has been allocated... allocate one now */
 
       paddr = mm_pgalloc(1);
       if (paddr)
         {
+          /* Determine page table flags */
+
+          if (riscv_uservaddr(vaddr))
+            {
+              flags = MMU_UPGT_FLAGS;
+            }
+          else
+            {
+              flags = MMU_KPGT_FLAGS;
+            }
+
           /* Wipe the page and assign it */
 
           riscv_pgwipe(paddr);
-          mmu_ln_setentry(ptlevel, ptprev, paddr, vaddr, MMU_UPGT_FLAGS);
+          mmu_ln_setentry(ptlevel, ptprev, paddr, vaddr, flags);
         }
     }
 

arch/risc-v/src/common/riscv_mmu.h

@@ -59,6 +59,10 @@
 
 #define MMU_IO_FLAGS            (PTE_R | PTE_W | PTE_G)
 
+/* Flags for kernel page tables */
+
+#define MMU_KPGT_FLAGS          (PTE_G)
+
 /* Kernel FLASH and RAM are mapped globally */
 
 #define MMU_KTEXT_FLAGS         (PTE_R | PTE_X | PTE_G)