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Shortening the names a little.
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@mithro
mithro committed Aug 8, 2016
1 parent 80a4a34 commit 7bacc84
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Showing 2 changed files with 37 additions and 37 deletions.
36 changes: 18 additions & 18 deletions targets/atlys_base.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -59,12 +59,12 @@ def __init__(self, platform, clk_freq):
pll_lckd = Signal()
pll_fb = Signal()

unbuffered_sdram_full = Signal()
unbuffered_sdram_half_a = Signal()
unbuffered_sdram_half_b = Signal()
unbuffered_encoder = Signal()
unbuffered_sys = Signal()
unbuffered_base50 = Signal()
unbuf_sdram_full = Signal()
unbuf_sdram_half_a = Signal()
unbuf_sdram_half_b = Signal()
unbuf_encoder = Signal()
unbuf_sys = Signal()
unbuf_base50 = Signal()

self.specials.pll = Instance(
"PLL_ADV",
Expand All @@ -83,22 +83,22 @@ def __init__(self, platform, clk_freq):
p_CLK_FEEDBACK="CLKFBOUT",
p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
# (400MHz) sdram wr rd
o_CLKOUT0=unbuffered_sdram_full, p_CLKOUT0_DUTY_CYCLE=.5,
o_CLKOUT0=unbuf_sdram_full, p_CLKOUT0_DUTY_CYCLE=.5,
p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//4,
# ( 66MHz) encoder
o_CLKOUT1=unbuffered_encoder, p_CLKOUT1_DUTY_CYCLE=.5,
o_CLKOUT1=unbuf_encoder, p_CLKOUT1_DUTY_CYCLE=.5,
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=6,
# (200MHz) sdram_half - sdram dqs adr ctrl
o_CLKOUT2=unbuffered_sdram_half_a, p_CLKOUT2_DUTY_CYCLE=.5,
o_CLKOUT2=unbuf_sdram_half_a, p_CLKOUT2_DUTY_CYCLE=.5,
p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=p//2,
# (200MHz) off-chip ddr
o_CLKOUT3=unbuffered_sdram_half_b, p_CLKOUT3_DUTY_CYCLE=.5,
o_CLKOUT3=unbuf_sdram_half_b, p_CLKOUT3_DUTY_CYCLE=.5,
p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=p//2,
# ( 50MHz) base50
o_CLKOUT4=unbuffered_base50, p_CLKOUT4_DUTY_CYCLE=.5,
o_CLKOUT4=unbuf_base50, p_CLKOUT4_DUTY_CYCLE=.5,
p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1,
# ( 50MHz) sysclk
o_CLKOUT5=unbuffered_sys, p_CLKOUT5_DUTY_CYCLE=.5,
o_CLKOUT5=unbuf_sys, p_CLKOUT5_DUTY_CYCLE=.5,
p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1,
)
# power on reset?
Expand All @@ -109,32 +109,32 @@ def __init__(self, platform, clk_freq):
self.specials += AsyncResetSynchronizer(self.cd_por, reset)

# sys
self.specials += Instance("BUFG", i_I=unbuffered_sys, o_O=self.cd_sys.clk)
self.specials += Instance("BUFG", i_I=unbuf_sys, o_O=self.cd_sys.clk)
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0))

# base50
self.specials += Instance("BUFG", i_I=unbuffered_base50, o_O=self.cd_base50.clk)
self.specials += Instance("BUFG", i_I=unbuf_base50, o_O=self.cd_base50.clk)

# encoder
self.specials += Instance("BUFG", i_I=unbuffered_encoder, o_O=self.cd_encoder.clk) # 66 MHz
self.specials += Instance("BUFG", i_I=unbuf_encoder, o_O=self.cd_encoder.clk) # 66 MHz
self.specials += AsyncResetSynchronizer(self.cd_encoder, self.cd_sys.rst)

# SDRAM clocks
# ------------------------------------------------------------------------------
# sdram_full
self.specials += Instance("BUFPLL", p_DIVIDE=4,
i_PLLIN=unbuffered_sdram_full, i_GCLK=self.cd_sys.clk,
i_PLLIN=unbuf_sdram_full, i_GCLK=self.cd_sys.clk,
i_LOCKED=pll_lckd, o_IOCLK=self.cd_sdram_full_wr.clk,
o_SERDESSTROBE=self.clk4x_wr_strb)
self.comb += [
self.cd_sdram_full_rd.clk.eq(self.cd_sdram_full_wr.clk),
self.clk4x_rd_strb.eq(self.clk4x_wr_strb),
]
# sdram_half
self.specials += Instance("BUFG", i_I=unbuffered_sdram_half_a, o_O=self.cd_sdram_half.clk)
self.specials += Instance("BUFG", i_I=unbuf_sdram_half_a, o_O=self.cd_sdram_half.clk)
clk_sdram_half_shifted = Signal()
self.specials += Instance("BUFG", i_I=unbuffered_sdram_half_b, o_O=clk_sdram_half_shifted)
self.specials += Instance("BUFG", i_I=unbuf_sdram_half_b, o_O=clk_sdram_half_shifted)

output_clk = Signal()
clk = platform.request("ddram_clock")
Expand Down
38 changes: 19 additions & 19 deletions targets/opsis_base.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -65,12 +65,12 @@ def __init__(self, platform, clk_freq):
pll_lckd = Signal()
pll_fb = Signal()

unbuffered_sdram_full = Signal()
unbuffered_sdram_half_a = Signal()
unbuffered_sdram_half_b = Signal()
unbuffered_encoder = Signal()
unbuffered_sys = Signal()
unbuffered_sys2x = Signal()
unbuf_sdram_full = Signal()
unbuf_sdram_half_a = Signal()
unbuf_sdram_half_b = Signal()
unbuf_encoder = Signal()
unbuf_sys = Signal()
unbuf_sys2x = Signal()

self.specials.pll = Instance(
"PLL_ADV",
Expand All @@ -89,22 +89,22 @@ def __init__(self, platform, clk_freq):
p_CLK_FEEDBACK="CLKFBOUT",
p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
# (800MHz) sdram wr rd
o_CLKOUT0=unbuffered_sdram_full, p_CLKOUT0_DUTY_CYCLE=.5,
o_CLKOUT0=unbuf_sdram_full, p_CLKOUT0_DUTY_CYCLE=.5,
p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//8,
# ( 66MHz) encoder
o_CLKOUT1=unbuffered_encoder, p_CLKOUT1_DUTY_CYCLE=.5,
o_CLKOUT1=unbuf_encoder, p_CLKOUT1_DUTY_CYCLE=.5,
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=6,
# (400MHz) sdram_half - sdram dqs adr ctrl
o_CLKOUT2=unbuffered_sdram_half_a, p_CLKOUT2_DUTY_CYCLE=.5,
o_CLKOUT2=unbuf_sdram_half_a, p_CLKOUT2_DUTY_CYCLE=.5,
p_CLKOUT2_PHASE=230., p_CLKOUT2_DIVIDE=p//4,
# (400MHz) off-chip ddr
o_CLKOUT3=unbuffered_sdram_half_b, p_CLKOUT3_DUTY_CYCLE=.5,
o_CLKOUT3=unbuf_sdram_half_b, p_CLKOUT3_DUTY_CYCLE=.5,
p_CLKOUT3_PHASE=210., p_CLKOUT3_DIVIDE=p//4,
# (100MHz) sys2x
o_CLKOUT4=unbuffered_sys2x, p_CLKOUT4_DUTY_CYCLE=.5,
o_CLKOUT4=unbuf_sys2x, p_CLKOUT4_DUTY_CYCLE=.5,
p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//2,
# ( 50MHz) base50 / sys
o_CLKOUT5=unbuffered_sys, p_CLKOUT5_DUTY_CYCLE=.5,
o_CLKOUT5=unbuf_sys, p_CLKOUT5_DUTY_CYCLE=.5,
p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1,
)
# power on reset?
Expand All @@ -115,36 +115,36 @@ def __init__(self, platform, clk_freq):
self.specials += AsyncResetSynchronizer(self.cd_por, reset)

# sys
self.specials += Instance("BUFG", i_I=unbuffered_sys, o_O=self.cd_sys.clk)
self.specials += Instance("BUFG", i_I=unbuf_sys, o_O=self.cd_sys.clk)
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0))

# base50
self.specials += Instance("BUFG", i_I=unbuffered_sys, o_O=self.cd_base50.clk)
self.specials += Instance("BUFG", i_I=unbuf_sys, o_O=self.cd_base50.clk)

# sys2x
self.specials += Instance("BUFG", i_I=unbuffered_sys2x, o_O=self.cd_sys2x.clk)
self.specials += Instance("BUFG", i_I=unbuf_sys2x, o_O=self.cd_sys2x.clk)
self.specials += AsyncResetSynchronizer(self.cd_sys2x, ~pll_lckd | (por > 0))

# encoder
self.specials += Instance("BUFG", i_I=unbuffered_encoder, o_O=self.cd_encoder.clk) # 66 MHz
self.specials += Instance("BUFG", i_I=unbuf_encoder, o_O=self.cd_encoder.clk) # 66 MHz
self.specials += AsyncResetSynchronizer(self.cd_encoder, self.cd_sys.rst)

# SDRAM clocks
# ------------------------------------------------------------------------------
# sdram_full
self.specials += Instance("BUFPLL", p_DIVIDE=4,
i_PLLIN=unbuffered_sdram_full, i_GCLK=self.cd_sys2x.clk,
i_PLLIN=unbuf_sdram_full, i_GCLK=self.cd_sys2x.clk,
i_LOCKED=pll_lckd, o_IOCLK=self.cd_sdram_full_wr.clk,
o_SERDESSTROBE=self.clk8x_wr_strb)
self.comb += [
self.cd_sdram_full_rd.clk.eq(self.cd_sdram_full_wr.clk),
self.clk8x_rd_strb.eq(self.clk8x_wr_strb),
]
# sdram_half
self.specials += Instance("BUFG", i_I=unbuffered_sdram_half_a, o_O=self.cd_sdram_half.clk)
self.specials += Instance("BUFG", i_I=unbuf_sdram_half_a, o_O=self.cd_sdram_half.clk)
clk_sdram_half_shifted = Signal()
self.specials += Instance("BUFG", i_I=unbuffered_sdram_half_b, o_O=clk_sdram_half_shifted)
self.specials += Instance("BUFG", i_I=unbuf_sdram_half_b, o_O=clk_sdram_half_shifted)

output_clk = Signal()
clk = platform.request("ddram_clock")
Expand Down

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